We are using the Transceiver Native PHY Intel Arria 10 FPGA IP.
We configured two RX PHY for the same Arria 10 FPGA device, one is 20bits (see the attached picture 20bits.jpg) and another one is 16bits (see the attached picture 16bits.jpg).
The 20bits RX PHY works without problem, but frequently the PLL lock signal of 16bits RX PHY is low, it can't be locked, as shown in picture PLL_lock_signal.jpg, you can see the signal with blue color.
Are there any special considerations when we configuring it to 16bits RX PHY?
Thanks in advance.
We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you