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Question about Transceiver Native PHY Intel Arria 10 FPGA IP

BXia
Novice
348 Views

Hi,

 

We are using the Transceiver Native PHY Intel Arria 10 FPGA IP.

 

We configured two RX PHY for the same Arria 10 FPGA device, one is 20bits (see the attached picture 20bits.jpg) and another one is 16bits (see the attached picture 16bits.jpg).

 

The 20bits RX PHY works without problem, but frequently the PLL lock signal of 16bits RX PHY is low, it can't be locked, as shown in picture PLL_lock_signal.jpg, you can see the signal with blue color.

 

Are there any special considerations when we configuring it to 16bits RX PHY?

 

Thanks in advance.

 

 

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3 Replies
BXia
Novice
212 Views

Hi @intel

Could you look into this case and share any advice?

Thanks.

Ash_R_Intel
Employee
199 Views

Hi,


Can you share the piece of your design Quartus archive? We need to check other IP settings as well.


Regards



Ash_R_Intel
Employee
167 Views

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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