I am currently attempting to take in 4 bit RGMII data into my system and then modify the resulting 32 bit AvalonST data. My testbench sends this data currently and it appears as RGMII inputs (enet_rx_d) but it does not get passed to the AvalonST signals. I have taken a screenshot of my platform designer design as well as my simulation. These are all instantiated after using the platform designer instantiation template.
Thanks in advance.
If I understand you correctly, basically your issue is you have send it data traffic to RGMII Rx interface of TSE MAC IP but nothing come out from TSE IP Avalon ST Rx interface to user logic design, right ?
I looked into your sim waveform and I can see that a lot of red colour signal which looks like your TSE IP is not initialized properly, including both reset signal. (enet_resetn and phy_resetn).
Just wonder did you initialized all your input signal (set some default value to all input signals) of your test bench before you start sim data traffic flow ?
Also, I have commented in your other forum post that perhaps it's good idea to checkout some TSE example design as reference.
I understand that you also contacted Arrow dFAE (Andy) for this TSE IP debug support and you also have another forum case regarding the reg_busy stuck issue.
May I suggest we consolidate all the issue into just one support case (Andy's case) for ease of discussion and debug while I close these 2 Forum cases ?
Thanks. Your sim waveform looks much better now.
- Again, my first question back to you is still have you generated one TSE sim example design as golden reference for that it's easier to compare the reference sim result with your design sim result.
- For your sim debug, you can checkout following suggestion
- Have you run the sim longer to double confirm there is really nothing coming out to Avalon ST Rx interface ? Are you using internal FIFO in cut through mode or store and forward mode ?
- Also, just curious. Is the reg_busy issue resolved now ? Meaning you are able to configure TSE IP correctly now or else it won't work correctly
- You can review the chapter 5.3.1 (page 101) to ensure you initialize TSE IP correctly for RGMII configuration (watch out on TSE MAC reset condition and also TX, RX path enable condition)
Hi again dlim,
Your first statement regarding Arrow and the reg_busy issue is correct. We can combine these two if you'd like. Would I need to do that?
Firstly, my reg_busy issue has been mostly resolved. I would like to focus on solving that and then moving on to the Avalon issue (if it persists). The FSM which configures the registers is being entered and I would like to monitor the behavior, but the configuration is done before the waveforms appear in simulation (the signals show as "-No Data-"). I could get around this by repeatedly entering the FSM but do not want to do that in the final design. Is there a way to start up each module simultaneously so that this offset doesn't exist? Attached is an example of this. I drive the FSM with the reg_clk.
To answer your other questions:
- I have been able to generate an example which uses one Ethernet port.
- My current design was in cut-through mode but is now in store and forward mode (Rx_almost_empty and Tx_section_full being set to '0' in my configuration).
- I am using "run -all" for simulation duration.
You don't need to do anything extra in these 2 forum cases. Let me help you.
Below is what I am going to do.
- I will copy over your latest debug discussion into support case opened by Andy (Arrow dFAE)
- Then, I will close these 2 forum case to avoid confusion
- After that, we all can move on to discuss debug plan in Andy's case.
Btw, you have the right mindset in moving the debug plan
- It's good to know reg_busy is no longer stuck high. Let's resolve whatever issue that you may have with Avalon configuration bus as it's essential to configure TSE IP correctly first before we look into functionality issue
- Once we sorted out all the configuration issue then we can look into the Avalon ST RX interface no data coming out issue