I am currently attempting to take in 4 bit RGMII data into my system and then modify the resulting 32 bit AvalonST data. My testbench sends this data currently and it appears as RGMII inputs (enet_rx_d) but it does not get passed to the AvalonST signals. I have taken a screenshot of my platform designer design as well as my simulation. These are all instantiated after using the platform designer instantiation template.
Thanks in advance.
If I understand you correctly, basically your issue is you have send it data traffic to RGMII Rx interface of TSE MAC IP but nothing come out from TSE IP Avalon ST Rx interface to user logic design, right ?
I looked into your sim waveform and I can see that a lot of red colour signal which looks like your TSE IP is not initialized properly, including both reset signal. (enet_resetn and phy_resetn).
Just wonder did you initialized all your input signal (set some default value to all input signals) of your test bench before you start sim data traffic flow ?
Also, I have commented in your other forum post that perhaps it's good idea to checkout some TSE example design as reference.
Yes my issue is that I have RGMII data coming in but the Avalon-ST RX interface does not receive it.
I have everything initialized and cleaned up in this simulation but the issue remains.
I understand that you also contacted Arrow dFAE (Andy) for this TSE IP debug support and you also have another forum case regarding the reg_busy stuck issue.
May I suggest we consolidate all the issue into just one support case (Andy's case) for ease of discussion and debug while I close these 2 Forum cases ?
Thanks. Your sim waveform looks much better now.
Hi again dlim,
Your first statement regarding Arrow and the reg_busy issue is correct. We can combine these two if you'd like. Would I need to do that?
Firstly, my reg_busy issue has been mostly resolved. I would like to focus on solving that and then moving on to the Avalon issue (if it persists). The FSM which configures the registers is being entered and I would like to monitor the behavior, but the configuration is done before the waveforms appear in simulation (the signals show as "-No Data-"). I could get around this by repeatedly entering the FSM but do not want to do that in the final design. Is there a way to start up each module simultaneously so that this offset doesn't exist? Attached is an example of this. I drive the FSM with the reg_clk.
To answer your other questions:
You don't need to do anything extra in these 2 forum cases. Let me help you.
Below is what I am going to do.
Btw, you have the right mindset in moving the debug plan
Hello, I also have the problem of reg_busy stuck at LL1. How can I solve it? Could you please redirecti me to Andy's case too? Thank you again. Marco.