RGMII interface on custom board

[Altera_Forum]

Hello everyone, 

 I'm trying to get the web server example design up and running on my custom board. I'm using the Micrel KSZ9021RL which has an RGMII interface. I've gotten to the point where it appears to be working in the Nios II Console but I get nothing on the RGMII tx lines when viewed in SignalTap. Here's what it's showing:  InterNiche Portable TCP/IP, v3.1 Copyright 1996-2008 by InterNiche Technologies. All rights reserved. prep_tse_mac 0 Can't read the MAC address from your board. We will assign you a MAC address. Your Ethernet MAC address is 00:07:ed:ff:cd:15 Static IP Address is 192.168.1.234 prepped 1 interface, initializing... INFO : TSE MAC 0 found at address 0x00022000 INFO : PHY Micrel KSZ9021RL found at PHY address 0x00 of MAC Group INFO : PHY - Automatically mapped to tse_mac_device INFO : PHY - Restart Auto-Negotiation, checking PHY link... INFO : PHY - Auto-Negotiation PASSED INFO : PHY - Checking link... INFO : PHY - Link established INFO : PHY - Speed = 100, Duplex = Full OK, x=51, CMD_CONFIG=0x00000000 MAC post-initialization: CMD_CONFIG=0x04000203 RX descriptor chain desc (1 depth) created mctest init called IP address of et1 : 192.168.1.234 Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) Created "web server" task (Prio: 4) Web Server starting up  Since I used the RGMII template, the -DTSE_MY_SYSTEM tag is in the BSP properties and the alt_tse_system_info structure has been created. I've also verfied that my transmit and receive clocks are present, currently 25 MHz for testing at 100 Mbps.  Does anyone have an idea on what I might be missing?  Thank you for looking! Scott

[Altera_Forum]

Are You sure the setup is OK? E.g. KSZ9021GN doesn't support PHY address 0.

[Altera_Forum]

Hi Socrates, 

 Thank you for your reply. I took a closer look at the data sheet and it does say that valid PHY address are in the range on 1-7. I changed the resistor configuration and it is now at address 0x01 but it still appears to perform the same way, the console says it's running but I see nothing on the RGMII lines or in Wireshark. The MDIO interface seems to work perfectly. I'll keep at it.  Thanks again, Scott

[Altera_Forum]

Do You get any timing violations then? Is it only transmit path isn't working? If yes, then be sure You've constrained ALL the clocks properly. I had similar issues, when rx worked, but tx not.

[Altera_Forum]

It looks like I don't have any timing violations except the altera_reserved_tck but in looking more closely at TimeQuest, the sdc file associated with the Ethernet interface is having problems finding a few critical clocks. This could definitely be my problem if some of the clocks were removed somewhere along the line. Hopefully the answer isn't buried too deeply in the compilation report. Thanks again for the help. 

 Warning: Ignored filter at gtp_qsys_ethernet_tse_mac_constraints.sdc(146): clk could not be matched with a port Warning: Ignored create_clock at gtp_qsys_ethernet_tse_mac_constraints.sdc(146): Argument <targets> is an empty collection Warning: Ignored filter at gtp_qsys_ethernet_tse_mac_constraints.sdc(149): ff_tx_clk could not be matched with a port Warning: Ignored create_clock at gtp_qsys_ethernet_tse_mac_constraints.sdc(149): Argument <targets> is an empty collection Warning: Ignored filter at gtp_qsys_ethernet_tse_mac_constraints.sdc(150): ff_rx_clk could not be matched with a port Warning: Ignored create_clock at gtp_qsys_ethernet_tse_mac_constraints.sdc(150): Argument <targets> is an empty collection Warning: Ignored filter at gtp_qsys_ethernet_tse_mac_constraints.sdc(153): tx_clk could not be matched with a port Warning: Ignored create_clock at gtp_qsys_ethernet_tse_mac_constraints.sdc(153): Argument <targets> is an empty collection Warning: Ignored filter at gtp_qsys_ethernet_tse_mac_constraints.sdc(154): rx_clk could not be matched with a port Warning: Ignored create_clock at gtp_qsys_ethernet_tse_mac_constraints.sdc(154): Argument <targets> is an empty collection

[Altera_Forum]

Firstly define Your input clocks properly. Then use propagate all generated clocks and check what You have.

[Altera_Forum]

For some reason, the whole TX MAC interface is gone post fit. All that's left of the RX side is ff_rx_data, ff_rx_eop, ff_rx_mod, and ff_rx_sop. If I look at the chip planner to see what clock is driving the rx registers, it's on Open Core clock as shown below. I don't see any messages saying that it synthesized out some of the logic. The Qsys project was based on a reference design so it looks okay. They always make it look so easy... 

 |GTP|pzdyqx:nabboc|pzdyqx_impl:pzdyqx_impl_inst|MDCK2395:\stratixiii_WCRO7487_gen_0:stratixiii_WCRO7487_gen_1|WCRO7487_0

[Altera_Forum]

removed signals ar caused by unconnected nets. E.g. clocks, clock enables, signal enables, etc...

[Altera_Forum]

Hi Scott, 

 This is an old post, but I am having the same problem that you describe here. I'm trying to get the example SSH or web server up and running on my own hardware. I too see data coming back on the Rx, but nothing going out on the Tx.  I have bought the TSE from Altera. I have the same KSZ9021RL chip and I have modified the drivers to seemingly talk correctly to the chip to configure it.  Did you ever solve this?  Thanks, Dan

[Altera_Forum]

Hi Dan, 

 That was a while back but if I remember correctly, I didn't get past this problem.  One thing I have had luck with is a VHDL MAC and stack from comblock.com. It's designed to work with that same phy so it's configured correctly for the hardware from the beginning. Both pieces worked pretty much out of the box in a very controlled test. I was able to open up a socket and transfer a pretty large block of data in and out. It being pretty low level, there are several features that aren't included as indicated in their documents. It's been a low priority so I haven't really gotten back to it since proving my hardware worked.  Hope this helps. If you end up getting the Altera MAC working with the Micrel device, I'd love to see what the problem ended up being. I'm sorry I couldn't help more.  Good luck, Scott

[Altera_Forum]

Did You copy required file for RGMII from example project? It's somehow related to SGDMA afaik.

[Altera_Forum]

Probably not. What RGMII example project? I have seen and tried several, but I haven't combined any. 

 I'm confused with one having scatter gather interfaces to the TSE and another reference project has packet sink and source. Which one do I need? I was about to put the packet sink in place of the scattergather. The manual shows scatter gather.

[Altera_Forum]

Start Eclipse, create a new project from example projects and choose either web server (RGMII) or simple socket server (RGMII) example. It will create a new project and there will be a file called "tse_my_system.c". Copy it to Your project directory. 

Or You can create a new .c file and add the same contents to it:   /* REQUIRED ONLY IF NETWORK IS RGMII */ # ifdef ALT_INICHE # include "ipport.h"# endif # include "system.h"# include "altera_avalon_tse.h"# include "altera_avalon_tse_system_info.h" alt_tse_system_info tse_mac_device = { TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(TSE_MAC, 0, SGDMA_TX, SGDMA_RX, TSE_PHY_AUTO_ADDRESS, &marvell_cfg_rgmii, DESCRIPTOR_MEMORY) };   Then remember to edit this file and add your initialization stuff instead of Marvell structure.

[Altera_Forum]

Yes, I used those examples. I had to modify this file to point to my TSE, SGDMA, descriptor memory etc. It seems to talk to the TSE just fine to control it, I just don't have any packets coming out of the TSE to the phy. I see packets coming from the network through the phy to the TSE, just not out of the TSE.  

 My output looks pretty much like Scott's did, only it sees the phy at [6] like it should from the jumpers, it is 1000Mbs(as it should) . It can also sense correctly the 10/100/1000 speed interface that the phy negotiates on it's own as I change network speed(different routers). Since it doesn't have [packets going out, DHCP doesn't work, neither does a static IP though.