Re: RTL simulation with symbol converted in HDL

Altera_Forum · ‎08-27-2010

I have a simple project with a single schematic file that uses the 7493 counter taken from the "others | maxplus" library of symbols.

It's a TTL numerated symbol that maps the old TTL discrete logic circuits.

In order to simulate it I do the following:

1)

"File | Create/update | HDL from current file" to generate the Verilog code of the circuit

2)

Add a Verilog test bench

3)

Remove the .bdf file from the project and add the Verilog version of it.

Now the project is composed by two Verilog files (project and test bench)

After compiling the project (that synthesizes without errors) I can run a gate level simulation. Unfortunately I cannot run an RTL

simulation since I don't have the Verilog file for the 7493 component.

What I can do in order to run both RTL and gate level simulations for a project that uses these kind of library components?

Thx.

Altera_Forum · ‎08-27-2010

my guess is that the maxplus library might be originally written in AHDL which is why a gate level simulation works. you may only the have option of a post-map and a gate level simulation

what's inside the generated Verilog file?

Altera_Forum · ‎08-27-2010

The generated code is the following.

It recalls a strange \7493 component.

Could be the backslash the problem?

Is backslash allowed in Verilog code?

module counter_x7493(
 Reset,
 Clk,
 Q3,
 Q2,
 Q1,
 Q0
);
input wire Reset;
input wire Clk;
output wire Q3;
output wire Q2;
output wire Q1;
output wire Q0;
wire SYNTHESIZED_WIRE_0;
assign Q0 = SYNTHESIZED_WIRE_0;
 
\7493  b2v_inst(
 .RO1(Reset),
 .RO2(Reset),
 .CLKA(Clk),
 .CLKB(SYNTHESIZED_WIRE_0),
 .QC(Q2),
 .QB(Q1),
 .QA(SYNTHESIZED_WIRE_0),
 .QD(Q3));
endmodule

Altera_Forum · ‎08-27-2010

looks like i was wrong, the original source is in .bdf not AHDL, this doesn't seem so bad

if you go to $QUARTUS_ROOTDIR/libraries/other/maxplus2 you'll find 7493.bdf. if you open it up you'll see the component's source. go to File > Create > Create HDL for current file and create a Verilog file. when you create the .v from the 7493.bdf in you get the following warning explaining the slash:

Warning: Design name for "7493" contains a number -- illegal for Verilog HDL and VHDL -- adding "\" in front of name

the 7493.v file looks like its just HDL for the .bdf, it doesn't instantiate any other components. add the file to your project, and Quartus should use this instead of the .bdf to compile your design, which should allow use in ModelSim (i didn't try vsim). if it doesn't work in ModelSim, rename the module from \7493 to my7493 and rename the instantiation and that should fix it

Altera_Forum · ‎08-27-2010

Thanks Thepancake,

I followed your detailed instructions and everything works fine.

It has not been necessary to rename the 7493 Verilog instance.

Altera_Forum · ‎08-27-2010

cool :)

you could write a script to dump all of those .bdf files to Verilog to save some time in the future