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RapidIO II IP core with management module disabled

Altera_Forum
Honored Contributor II
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I have instantiated a RapidIO II IP core and unchecked the "Enable Maintenance module" checkbox. For some reason, the maintenance module Avalon-MM master port (mnt_master) still exists in the instantiated IP. Is there a reason for this? I just want to make sure that I do not need to implement something in my logic to interact with this port. I do not plan on using maintenance requests in my implementation. 

 

FWIW, I am using a Cyclone V SX SoC. I am using Altera Quartus II SJ 15.0.2 and implementing my design (along with this IP core) in Qsys.
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