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Altera_Forum
Honored Contributor I
1,115 Views

Reg AN427 Example Design on Quartus 9 WE

I like ur input reg VIP example design: AN427 on cycloneIII EP3C120 

 

I tried to synthesize and create programming file instead of the provided sof file. But the Analysis & Synthesis result reports following warnings like 

Warning: Can't analyze file -- file <path_name>/vip_example_design_3c120_v90_revA/ip/altera_avalon_i2c/i2c_master_byte_ctrl.vhd is missing. 

Also i2c_master_top, bit_ctrl vhdl files r missing though it is included in Project & shown in Project Navigator/files. Plz guide me.
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5 Replies
Altera_Forum
Honored Contributor I
70 Views

Ok. I tried creating a similar design with same settings & synthesised after assigning pins. When running Analysis & Synthesis i got warnings: 

 

Warning: Assertion warning: Ignoring parameter INDATA_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone III of altsyncram megafunction cannot use input registers with clear signals 

 

Warning: Assertion warning: Ignoring parameter WRCONTROL_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone III of altsyncram megafunction cannot use input registers with clear signals 

 

And while running I/O Assignment Analysis, i get errors: 

Error: Can't place multiple pins assigned to pin location Pin_F4 (IOPAD_X0_Y65_N21) 

Info: Pin BITEC_DVI_IO_OUT_DVI_ISEL is assigned to pin location Pin_F4 (IOPAD_X0_Y65_N21) 

Info: Pin ~ALTERA_ASDO_DATA1~ is assigned to pin location Pin_F4 (IOPAD_X0_Y65_N21) 

 

Error: Can't place multiple pins assigned to pin location Pin_E2 (IOPAD_X0_Y61_N14) 

Info: Pin BITEC_DVI_IO_OUT_DVI_DAT is assigned to pin location Pin_E2 (IOPAD_X0_Y61_N14) 

Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is assigned to pin location Pin_E2 (IOPAD_X0_Y61_N14) 

 

Please help me.
Altera_Forum
Honored Contributor I
70 Views

The first two warnings are assigned to particular RAM instances in your design. Check, why these instances apparently have settings, that are incompatible with Cyclone III. A warning doesn't prevent synthesis, so may simply ignore it. 

 

The two errors are causes by your FPGA device options settings. You must specify the configuration pins as regular I/O after configuration.
Altera_Forum
Honored Contributor I
70 Views

Thank you FvM! 

Sorry for the dalayed reply. I changed the FPGA configuration pin settings to regular I/O and was able to fit the design. 

 

The fitter shows Critical Warning: PLL clock inst|....|pll1|clk[1] not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. 

 

& warnings like: *alt_vip_IS2Vid:*|is_serial_output 

[*] could not be matched with a keeper. (filter problem-mismatch) 

 

After simulating altpll in Modelsim, the transcript msg reads 

Note: Cyclone III PLL locked to incoming clock 

 

I'm not familiar with pll & VIP suite and learning it. Kindly guide me.
Altera_Forum
Honored Contributor I
70 Views

How do I set configuration pins?? I have the same kind of error message. ~ALTERA_ASDO_DATA1~ doesn't appear in my pin planner or assignment editor...  

 

Info: Pin da[0] is assigned to pin location Pin_F4 (IOPAD_X0_Y65_N21) 

Info: Pin ~ALTERA_ASDO_DATA1~ is assigned to pin location Pin_F4(IOPAD_X0_Y65_N21) 

 

I'm using the cyclone III 3C120 dev. kit.
Altera_Forum
Honored Contributor I
70 Views

HI freelancer, 

 

on tab "Assignments" click on "Device". Next click on "Device and Pin Options...". On the opening window choose "Dual-Purpose Pins". 

Here you can set the state of them.
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