FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Reg :VIP suite

SDasa2
New Contributor I
819 Views

Hi Sir,

How to read frame buffer contents?

I have to read the frame and process it and write the processed frame to frame buffer again in NIOS2 ECLLIPSE .

 

where can i get the brief description for VIP based nios2 functions and parameters?

 

 

 

 

 

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Ahmed_H_Intel1
Employee
683 Views

Hi,

Did you check the available examples for VIP on our design store? Please check the following and let me know if this was useful for you.

https://fpgacloud.intel.com/devstore/?search=VIP

Regards,

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SDasa2
New Contributor I
683 Views
Dear Sir, I worked on AN 776 uhd video reference design with the development kit ARRIA10GX . The source is from Graphics Card and Destination 4K TV. the display is coming on the TV. now from that design i need only CLOCKED VIDEO INPUT and FRAME BUFFER and CLOCKED VIDEO OUTPUT and other I2C peripherals. so i want to read the frame data RGB DATA and do some modifications on that frame data and rewrite back that data . How can i access frame buffer contents for our customization?
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Ahmed_H_Intel1
Employee
683 Views

Where you store this frame buffer? On-chip memory or external RAM?

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SDasa2
New Contributor I
683 Views
Please see the attached functional diagram.It is our requirement. Please provide your guidance for the following required functional implementation. 1. Frame Buffer Accessing in the VIP Control Source code for implementation of our customized conversion. 2. Brief description for VIP based nios2 functions and passing parameters. Functionalities to be implemented in the FPGA: 1. Display Data receiving from HDMI Receiver. 2. Stored Frame content from DDR4 sdram to be retrieved. 3. Implementation of customized conversion process. 4.Storage of conversion data to DDR4 sdram. 5. Sending converted video data to HDMI Transmitter. Thanks and regrds D.SUVARNA
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SDasa2
New Contributor I
683 Views

Please see the attached functional diagram.It is our requirement.

Please provide your guidance for the following required functional implementation.

1. Frame Buffer Accessing in the VIP Control Source code for implementation of our customized conversion.

2. Brief description for VIP based nios2 functions and passing parameters.

 

Functionalities to be implemented in the FPGA:

1. Display Data receiving from HDMI Receiver.

2. Stored Frame content from DDR4 sdram to be retrieved.

3. Implementation of customized conversion process.

4.Storage of conversion data to DDR4 sdram.

5. Sending converted video data to HDMI Transmitter.

 

Pls guide me .

 

Thanks and regrds

D.SUVARNAprocess flow diagram.jpg

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