Resource utilization of a 32-bit DDR3 controller in Cyclone 10 GX

[pgigliotti_uasc]

I am looking for documentation that shows the resource utilization of a 32-bit DDR3 controller in Cyclone 10 GX .

[Rashmi1]

Hi Paul,

Please refer to EMIF C10 GX FPGA IP User guide. Link for the document: https://www.intel.com/content/www/us/en/programmable/documentation/mls1506089797502.html

Refer to section 3: Intel Cyclone 10 GX EMIF IP Product Architecture , it goes over resource sharing .

Section : 3.1.4.2 goes over implementing a X72 interface for example. We do not have anything to explain X32 i our documentation.

Thanks,

Intel Forum Support