I am looking for documentation that shows the resource utilization of a 32-bit DDR3 controller in Cyclone 10 GX .
Please refer to EMIF C10 GX FPGA IP User guide. Link for the document: https://www.intel.com/content/www/us/en/programmable/documentation/mls1506089797502.html
Refer to section 3: Intel Cyclone 10 GX EMIF IP Product Architecture , it goes over resource sharing .
Section : 184.108.40.206 goes over implementing a X72 interface for example. We do not have anything to explain X32 i our documentation.
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