FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5914 Discussions

SD SDI output not working

Honored Contributor II

My design consists of the following IP blocks , and I have not been able to make it to work (no image output). The design objective is to convert 20 bits progressive parallel data to SD SDI and display on the SDI monitor. Could somebody please take a look at my blocks below to see what I did wrong?  

They are connected in order from 1 - 4. 


Thanks in advance. 



1. CVI (720x487- 20bit progressive parallel data , 27mhz pix clk, separate H-V sync inputs) >>> 


2. INTERLACER (20 bits IN-OUT via Avalon system clk = 27mhz) >> 


3. COLOR PLANE SEQUENCER (20bit parallel Y-C in to 10 bit sequence YCbYCr out via Avalon system clk = 27mhz) >> 


4. CVO (10 bit sequence in, vid clock=27mhz pix clk, preset to NTSC settings) 

Results: No image at the SDI output.
0 Kudos
1 Reply
Honored Contributor II

Hello Jimmy 


You could try to use the test_pattern_generator to feed the CVO only and see if it's working properly with your SDI output.