My design consists of the following IP blocks , and I have not been able to make it to work (no image output). The design objective is to convert 20 bits progressive parallel data to SD SDI and display on the SDI monitor. Could somebody please take a look at my blocks below to see what I did wrong?They are connected in order from 1 - 4. Thanks in advance. 1. CVI (720x487- 20bit progressive parallel data , 27mhz pix clk, separate H-V sync inputs) >>> 2. INTERLACER (20 bits IN-OUT via Avalon system clk = 27mhz) >> 3. COLOR PLANE SEQUENCER (20bit parallel Y-C in to 10 bit sequence YCbYCr out via Avalon system clk = 27mhz) >> 4. CVO (10 bit sequence in, vid clock=27mhz pix clk, preset to NTSC settings) Results: No image at the SDI output.