SDRAM Memory Controller

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

SDRAM Memory Controller

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Hi,

A newbie question.

I am using your SDRAM Controller without NIOS. Can someone give some help on how to read memory with the controller? I assume you switch the az_rd_n line down to enable it and then disable the write, but that doesn't seem to work for me at all.

Can some one provide an example with this component in Verilog?

Thanks!

Jack

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