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Altera_Forum
Honored Contributor I
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SerDes GX module doesn't see the GX clocking signal

Hello, 

 

I really am not sure this specific forum is the one in which my question best fits, so forgive me in case I'm doing wrong. 

 

I have created a module, which instantiates a GX SerDes module, in a plain VHDL architecture, on a "Cyclone IV". The compiler output is nice, and the code works in the device. 

 

In order to port it to another target, I tried to convert it to a nios ii device, in order to adress it from a C code. The module integrated in this NIOS is the same, and the target remains the same. However, the compiler output says : 

 

error (15065): clock input port inclk[0] of pll "cycloneiv_nios2:nios_inst|...gx_1|altpll pll0|altpll_mm81:auto_generated|pll1" 

must be driven by a non-inverted input pin or another pll, optionally through a clock control block 

info (15024): input port inclk[0] of node "cycloneiv_nios2:nios_inst|...altpll pll0|altpll_mm81:auto_generated|pll1" is not connected 

 

whereas I do am quite sure that the clock input pin specific to the GXB module is connected (checked in my different files from top pin assignment, to GXB SerDes instance of the ALTERA IP). 

 

The PLL instanciated by the GX module is the generic ALTERA file located in Qartus folders, from what I can check in the design hierarchy. 

 

Are there things to check in order that I investigate and correct this ? 

 

Quartus version is 12 build 263. and Qsys accordingly. The NIOS II architecture was generated with Qsys, and the generation report is just fine. The GXB module's RX, TX and PLL_IN_CLOCK have been made "conduit", in order to export them to the chip pins directly, and to minimize coupling with the NIOS. See architecture of the NIOS generated : 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=7553  

 

Please let me know where I made a mistake in the design. 

 

Let me know which information you need. 

 

Regards.
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Altera_Forum
Honored Contributor I
42 Views

I have solved my first problem 10 minutes ago. 

 

By the way, I now have another message during compiling : 

 

- the analysis is 100% Ok, but 

- the fitter cant place a clock pin on the pin which the board I'm using uses 

 

The error message is : 

 

Error (170084): Can't route signal "clock~input" to atom "clock~inputclkctrl" 

 

I obviously cant change the pin that the chip uses. Also, I have tried to put a pll inside the design, but it also fails during fitting. 

 

I'm relatively new to Quartus, so I would really appreciate if someone could explain me how to fit this clock in this design. 

 

I know the fitting with a pure hard coded VHDL system works. Maybe the NIOS processor puts too much requirements on the CycloneIV (115K LE). 

 

Please let me know. 

 

Regards.
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