FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
6114 Discussions

SERDES IP not compiling after migrating to Quartus Pro 23.1



I am using LVDS SERDES IP on Arria 10 for RX DPA-FIFO which works on Quartus Prime17.1. The input data are all located on bank 3 and the reference clock comes from the output of an IOPLL.

After migrating to Quartus Pro 23.1 it doesn’t compile anymore.

Error(18694): The reference clock on PLL"adc_if|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll",which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

Error: Failed to synthesize partition

It seems like the pin locations of data and clock are more restrictive in the newer version. It only compiles if the location of data pins are all in the same I/O bank and the clock comes from a dedicated clock pin from that same bank. It also fails if those pins are in the same bank number but different bank letter (e.g. 3D and 3F)

Error(14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 LVDS_CHANNEL(s)). Fix the errors described in the submessages, and then rerun the Fitter.


Is there a workaround to for this? Either to make it work within pins from the same bank number (different letter) or from the output of an IOPLL like in previous versions.


Thanks in advance

0 Kudos
5 Replies
New Contributor III

Error(14566) can be probably fixed by adding a Global Clock assignment to the dedicated clock pin. Error(18694) has been introduced in QPP 18.1, up to 18.0, SERDES refclock could be routed through core. You'll find all related forum discussion and support notes by searching for the error number.

As error message and forum statements suggest, Intel has blocked SERDES refclock routing in QPP to save the max data rate specification. I feel they threw the baby out with the bath water. Everybody knows that clock routing involves additional jitter, nevertheless it could be and has been widely used with Intel FPGA.

A possible solution could be that an option to enable refclock routing is disclosed to the public, to be used at your own risk. I bet that the option already exists, a cautious programmer won't cut existing functionality without creating a legacy option.


Thanks for your answer. 

Unfortunately the Error(14566) is not fixed by setting the reference clock as a global clock. Any other solutions to make the LVDS RX work among adjacent banks? Is it actually possible?

Where can I find this legacy option?

New Contributor III
I can confirm that the option exists, but I don't feel legitimated to publish it in the official Intel forum. You can ask your Intel FAE for support, or try to locate the solution in internet forums.

Sorry that I can't help this way


I guess it is not possible to make the LVDS RX work among adjacent banks as per the latest Handbook has mentioned this.

"For differential receivers, the PLL can drive only the channels within the same I/O bank."

You can refer to the link for more information:




New Contributor III

It's definitely not possible without setting a "magic" option that disables the "no dedicated reference clock" error.

Provided you know the option, it's your responsibility to check that the design can work reliably under the given conditions, means data rate is clearly below maximum. E.g. Arria is specified to support 1250  to 1600 MBPS, depending on the speed grade, but your application uses 500 or 800 MBPS.