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Beginner
170 Views

Serial Flash IP page program

This support request is a continuation of a previous post i made that i no longer have access to, with subject: What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?

Link:

https://supporttickets.intel.com/requestdetail?casenumber=04706540&lang=en-US

We are still having issues with accessing the EPCQL device of our Cyclone 10GX development board. Software cannot write to the EPCQL but we can read from it ( ID and data from EPCQL).  The path is through the PCIe bus - Avalon bus - Serial Flash IP.

Read and Page Program is OK if we go through JTAG Master IP.  

Attached is our code, which was requested by Intel from my original post.

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5 Replies
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Employee
160 Views

Hi,


There is no special way to access through the PCIe interface. You will need to make sure that you are accessing to the correct location of the Serial Flash IP.


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Beginner
154 Views

We think we are accessing the correct location.  We have used the JIC you've provided and the SW still doesn't work.  Do you see anything wrong with the code I have attached?

 

Thanks.

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Employee
148 Views

Hi,


I do not see any issue on the code. I would recommend you to try using SignalTap to check if the data is send correctly to the IP.


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Beginner
141 Views

Hi,

I currently don't have access to the board so we are trying to eliminate all possible issues we can think of.

An issue our SW team is seeing is that the status register shows that the Serial Flash IP appears to not receive or execute the page program command.  We find this odd considering we are able to read the flash ID and read from the flash device, which somehow eliminates Avalon bus issues.

Is there a good document we can follow on how to use the Serial Flash IP?  I have found conflicting documents/content especially on the Page Program sequence.

Thanks

 

 

 

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Employee
135 Views

Hi,


We only have the documentation from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-gen-sfi.pdf Chapter 1.8 which utilize Nios to performed the verification.


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