This support request is a continuation of a previous post i made that i no longer have access to, with subject: What's the EPCQL Page Program sequence when using Serial Flash IP on a Cyclone 10GX with PCIe core? Is there a special way when the IP is hooked up to the PCIe core Avalon bus?
We are still having issues with accessing the EPCQL device of our Cyclone 10GX development board. Software cannot write to the EPCQL but we can read from it ( ID and data from EPCQL). The path is through the PCIe bus - Avalon bus - Serial Flash IP.
Read and Page Program is OK if we go through JTAG Master IP.
Attached is our code, which was requested by Intel from my original post.