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Altera_Forum
Honored Contributor I
743 Views

Signal input for Video LVDS SERDES Transmitter/Receiver

I am using the Video LVDS SERDES Transmitter/Receiver from Microtronix Inc. The output signals make good sense as they are pins that connect to a TFT display.  

 

The input signals are just tx[27:0], this is for R(7..0), G(7..0), B(7..0), HSync, VSync, PClock, and Enable. What order should be these be in? 

 

If anyone has the datasheet I would be most glad. The technical docs link at http://www.altera.com/products/ip/dsp/additional_functions_dsp/m-mtx-lvds-serdes.html gives a 404 response. 

 

Thank you!! 

Steve
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2 Replies
Altera_Forum
Honored Contributor I
47 Views

Please see user manual at this link. 

 

http://www.microtronix.com/ip-cores/video-lvds-serdes-transmitter-receiver-ip-core 

 

28-bits will go like this: 

 

TX_OUT_A 

TX_OUT_B 

TX_OUT_C 

TX_OUT_D 

 

[6-0] 7-bits each. And there is Input side: 

 

RX_IN_A 

RX_IN_B 

RX_IN_C 

RX_IN_D 

 

Regards-
Altera_Forum
Honored Contributor I
47 Views

Thank you, that is exactly what I needed!

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