I am using C10 GX in custom board for TSE IP core.
My configuration is TSE + LVDS.
After download the image, the connection is not work.
From EDS, it prints out "PCS SGMII mode disabled" as attached below.Where I can find information to debug this?
To ensure we are on the same page, just would like to clarify if you are using HPS TSE IP or if you are using normal FPGA TSE IP? If you are using normal FPGA TSE IP, just wonder if you have had a chance to test enabling the SGMII_ENA register bit. You may refer to section 5.2.5. If_Mode Register (Word Offset 0x14) in the TSE user guide forfurther details.