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Stratix 10 H-Tile Avalon Streaming PCI Express Hard IP Core - app_init_rst

tm1701
Novice
725 Views

Hello,

 

the H-Tile Avalon Streaming PCI Express Hard IP-Core for the Stratix 10 device has a app_init_rst input port to "request for a hot reset to downstream devices".

  • When configured as Root-Port, is the input signal equivalent to the Secondary Bus Reset in the   Bridge Control Register of a Root Ports Configuration Space Header?
  • Are there any rules regarding how long the signal must be asserted to initiate a Hot-Reset to downstream devices?


The reason why I am asking is because asserting the signal for just one cycle in simulation has no effect and the PCIe specification states regarding the Secondary Bus Reset in the Bridge Control Register:
"Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification."

 

Thank you very much in advance!

 

Kind regards.

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1 Solution
wchiah
Employee
617 Views

Hi,


The H-Tile Avalon Streaming PCI Express Hard IP-Core for the Stratix 10 device is a specific piece of IP core, and its behavior may be influenced by the way it's configured and how it interacts with the PCIe protocol. However, I can provide you with some general information that might help you understand how this input port could be related to PCIe hot resets.

  1. app_init_rst Input: This input port seems to be related to initiating a hot reset to downstream devices. In PCIe, hot resets are used to reset and reinitialize the PCIe link without affecting the system's power. Typically, asserting such a signal would indeed be equivalent to triggering a hot reset in PCIe.
  2. Secondary Bus Reset (SBR): In the context of PCIe, the Secondary Bus Reset bit in the Bridge Control Register (BCR) of a Root Port Configuration Space Header is used to trigger a hot reset on the corresponding PCIe port. You're correct that the PCIe specification mandates a minimum reset duration (Trst) to ensure that the reset is effective. The duration of this reset signal should adhere to PCIe specification requirements.
  3. Duration of Reset Signal: The PCIe specification defines a minimum duration for the reset signal (Trst), which is necessary to guarantee that the reset reaches and is recognized by downstream devices. The duration may vary depending on the PCIe generation (e.g., PCIe 3.0, PCIe 4.0, etc.). To ensure that the reset is effective, you should consult the PCIe specification for the specific generation you are using and follow the guidelines provided there. It's essential to meet these timing requirements to ensure proper PCIe link recovery.

In your simulation, if asserting the app_init_rst signal for just one cycle has no effect, it might not meet the minimum reset duration requirements specified by PCIe.


Anyway I might be wrong also, but hope this information will give you some idea to move on.


Regards,

Wincent_Intel


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2 Replies
wchiah
Employee
618 Views

Hi,


The H-Tile Avalon Streaming PCI Express Hard IP-Core for the Stratix 10 device is a specific piece of IP core, and its behavior may be influenced by the way it's configured and how it interacts with the PCIe protocol. However, I can provide you with some general information that might help you understand how this input port could be related to PCIe hot resets.

  1. app_init_rst Input: This input port seems to be related to initiating a hot reset to downstream devices. In PCIe, hot resets are used to reset and reinitialize the PCIe link without affecting the system's power. Typically, asserting such a signal would indeed be equivalent to triggering a hot reset in PCIe.
  2. Secondary Bus Reset (SBR): In the context of PCIe, the Secondary Bus Reset bit in the Bridge Control Register (BCR) of a Root Port Configuration Space Header is used to trigger a hot reset on the corresponding PCIe port. You're correct that the PCIe specification mandates a minimum reset duration (Trst) to ensure that the reset is effective. The duration of this reset signal should adhere to PCIe specification requirements.
  3. Duration of Reset Signal: The PCIe specification defines a minimum duration for the reset signal (Trst), which is necessary to guarantee that the reset reaches and is recognized by downstream devices. The duration may vary depending on the PCIe generation (e.g., PCIe 3.0, PCIe 4.0, etc.). To ensure that the reset is effective, you should consult the PCIe specification for the specific generation you are using and follow the guidelines provided there. It's essential to meet these timing requirements to ensure proper PCIe link recovery.

In your simulation, if asserting the app_init_rst signal for just one cycle has no effect, it might not meet the minimum reset duration requirements specified by PCIe.


Anyway I might be wrong also, but hope this information will give you some idea to move on.


Regards,

Wincent_Intel


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wchiah
Employee
601 Views

Hi

 

Thanks for confirming the answer, glad that I am able to help you.

Hence, I will close my loop on this case and this thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

 

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

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