Stratix 10 L-Tile FPGA- Native PHY - PCS to PMA interface

[HBhat2]

Hi,

I planned to use PCS Direct between my custom PCS to PMA interface. Custom PCS works with TX_clkout frequency. So, there some cases where I may need to pause data for 1 cycle from Custom PCS to PMA, by de-asserting wr_en=0. As my custom PCS is running at the same frequency that of data-rate/DW, whenever I pause the data for 1 Cycle, there will be no data to serialize. How does the PMA take care this situation?

Also, whether the PMA logic checks the partial empty status to read out the data from fifo or it uses empty status to do so?

With regards,

HPB

[Nathan_R_Intel · Accepted solution]

Hie,

There is no PMA logic to check the status to read out the data from fifo when using PCS direct. You will need to implement the phase compensation fifo on your customer PCS.

The no data is present for 1 clock cycle, the serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data.

Regards,

Nathan

[HBhat2]

Hi @NathanR_Intel​ ,

Thank you for your response. I revisited the PMA blocks and agree with "Serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data." statement.

With regards,

HPB

[Nathan_R_Intel]

Hie,

Its good my explanation was clear enough to understand the serializer behavior.

Regards,

Nathan