FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5952 Discussions

Stratix 10 L-Tile FPGA- Native PHY - PCS to PMA interface

HBhat2
New Contributor II
604 Views

Hi,

 

I planned to use PCS Direct between my custom PCS to PMA interface. Custom PCS works with TX_clkout frequency. So, there some cases where I may need to pause data for 1 cycle from Custom PCS to PMA, by de-asserting wr_en=0. As my custom PCS is running at the same frequency that of data-rate/DW, whenever I pause the data for 1 Cycle, there will be no data to serialize. How does the PMA take care this situation?

Also, whether the PMA logic checks the partial empty status to read out the data from fifo or it uses empty status to do so?

 

With regards,

HPB

0 Kudos
1 Solution
Nathan_R_Intel
Employee
227 Views

Hie,

 

There is no PMA logic to check the status to read out the data from fifo when using PCS direct. You will need to implement the phase compensation fifo on your customer PCS.

The no data is present for 1 clock cycle, the serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data.

 

Regards,

Nathan

View solution in original post

3 Replies
Nathan_R_Intel
Employee
228 Views

Hie,

 

There is no PMA logic to check the status to read out the data from fifo when using PCS direct. You will need to implement the phase compensation fifo on your customer PCS.

The no data is present for 1 clock cycle, the serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data.

 

Regards,

Nathan

HBhat2
New Contributor II
227 Views

Hi @NathanR_Intel​ ,

 

Thank you for your response. I revisited the PMA blocks and agree with "Serializer will populate itself with all 0s or 1s for the 1 clock cycle. Its equivalent to releasing the PMA out of reset without sending data." statement.

 

With regards,

HPB

Nathan_R_Intel
Employee
227 Views

Hie,

 

Its good my explanation was clear enough to understand the serializer behavior.

 

Regards,

Nathan

Reply