Stratix 10 PCIe ST IP configuration errors

[agula]

Hello,

I am trying to implement a PCIe design on the Stratix 10 board but the bitstream stops at 71 % and give me an error saying the device is in configuration mode. I made sure that I am using the intel release IP and have connected it appropriately to the PCIe HIP through the ninit_done signal. The board is connected to the root complex of a PC when I try to program the device.

Thank you!

[KhaiChein_Y_Intel]

Hi,

Could you share the screenshot of the programmer and the error?

Thanks

Best regards,

KhaiY

[agula · Accepted solution]

The machine was causing the issue. Fixed by using a different machines PCIe port.

Thank you.

[KhaiChein_Y_Intel]

Hi,

I’m glad that the issue is resolved, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY

[agula]

Hi,

Is there anyway to circumvent Stratix 10 PCIe REFCLK requirements for configuration? The requirement is making the device not programmable on a server PCIe port. That particular machine works fine for Arria 10 PCIe designs. The PCIe slot is fully functional. The server is the only one with available virtualization support for the particular design. It would be great if there is some way to provide a separate reference clock. The issue is very frustrating as there should be no problem using the board on an extremely expensive server that has completely functional PCIe 3.0 compliant ports.  

Thanks