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hps ddr3

FPGA1
Novice
224 Views

hi

In HPS, I connect an Avalon-mm-bridge host to f2h-Axi-slave, and export the slave of Avalon-mm bridge from the machine. Can I read and write DDR3 on the HPS side directly?

0 Kudos
5 Replies
BrusC_Intel
Moderator
213 Views

Hello, FPGA1.


Thank you for posting in the Intel Community Support forum.


I will route your thread to a section for similar issues/questions so it can get answered as soon as possible.


Best regards,


Bruce C.

Intel Customer Support Technician


EBERLAZARE_I_Intel
188 Views

Hi,

It is recommended that you do all interconnect and bring it inside Platform Designer than exporting it out. If you are trying to access the DDR3 of the HPS , you will need a EMIF IP for the HPS and set the settings a per spec of your DDR connect it to the HPS.

EBERLAZARE_I_Intel
153 Views

Hi,


Any followup from your side?


FPGA1
Novice
127 Views

Hi,

Sorry, I just logged in today

I'm a little bit delayed now. I didn't continue with it

But I want to ask, can't Avalon mm bridge be imported from SoC system as data input on FPGA side? I just searched the EMIF IP, but I didn't find it. Can I explain this in detail

FPGA1
Novice
124 Views
Spoiler
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 I just went to cut a picture for you,We are eager to solve this problem ,thanks

097029d9f9d8f83c3b91d8964a05f6d.png
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