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Intel Customer Support Technician
It is recommended that you do all interconnect and bring it inside Platform Designer than exporting it out. If you are trying to access the DDR3 of the HPS , you will need a EMIF IP for the HPS and set the settings a per spec of your DDR connect it to the HPS.
Sorry, I just logged in today
I'm a little bit delayed now. I didn't continue with it
But I want to ask, can't Avalon mm bridge be imported from SoC system as data input on FPGA side? I just searched the EMIF IP, but I didn't find it. Can I explain this in detail