Stratix III DDR2 HPC&HPC II DQ/DQS/DM without output data problem!!

[Altera_Forum]

Environment: Stratix III EP3SL340F1517I3  

DDR2 SDRAM: M470T5663QZ(H)3 with 2G size(which has two ranks、64bits datawidth and two clocks)  Quartus II 9.1 sp2  My purpose:I want to generate a HPC or HPC II to validate whether my DDR2 is worked? Now the initialization is completed, but I have encountered other two problems:  (1) The DDR2 SDRAM has two ranks, can I use quartus II 9.1 to generate HPC for the DDR2 SDRAM, I heard someone said the HPC can not support Multi-rank DDR2 SDRAM, is that true?  (2) When I use HPC to test the DDR2 SDRAM above, I use quartus II 9.1 megacore manager to generate HPC including the example driver, the I follow the steps of the useguide to do the project, but I found there is no data output in the DQ/DQS/DQSN/DM signal(but the wdp_wdata3_1x/wdp_wdata2_1x/wdp_wdata1_1x/wdp_wdata1_1x and dio_rdata3_1x/dio_rdata2_1x/dio_rdata1_1x/dio_rdata0_1x signals which are IOE input are existed ):confused: ,and the command and address signal can be seen.   Then I changed the OCT, the DQ/DQS/DQSN/DM ouput termination, I change the series 50 ohm with calibration to series 50 ohm, the I see there are signal in the DQ/DQS/DQSN/DM pin, but have new problems, the local_rdata read out is not correct, there are many fff in it.  These problems confused my for a long time, I hope somebody can give me some advice, thanks!

[Altera_Forum]

1. HPC should handle multi-rank. You have to first tell it how many overall chip selects, then tell it how many of them are for multiple ranks. 

 2. You may not be completing calibration. Seems like when you disable the calibration, you see your data, but then the data is likely not properly calibrated to dqs. There is a signal that comes out of the controller called init_done. You can check to see if that is going high or staying low.

[Altera_Forum]

--- Quote Start ---  1. HPC should handle multi-rank. You have to first tell it how many overall chip selects, then tell it how many of them are for multiple ranks.  2. You may not be completing calibration. Seems like when you disable the calibration, you see your data, but then the data is likely not properly calibrated to dqs. There is a signal that comes out of the controller called init_done. You can check to see if that is going high or staying low.  --- Quote End ---   Ok, I see, thanks for you reply! You are right, the calibration was not done correctly. Problem has been solved. It is caused by the power supply of I/O voltage in the FPGA Board, during the initialization the current of the 1.8V is very high, so even the initial_done was going high(spending several seconds), but the 1.8V supply is abnormal during the initialization. So I increased the capacity of the 1.8V driving.  Thanks again!