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SThom66
Beginner
135 Views

Stratix V DDR3 simulation not working. All memory signals undefined.

I ran the tcl command to generate the simulation files and then followed the instructions to run the simulation:

 

To generate the VHDL example design, open the Quartus project "generate_sim_example_design.qpf" and

select Tools -> Tcl Scripts... -> generate_sim_vhdl_example_design.tcl and click "Run".

Alternatively, you can run "quartus_sh -t generate_sim_vhdl_example_design.tcl"

at a Windows or Linux command prompt.

 

The generated files will be found in the subdirectory "vhdl".

 

To simulate the example design using Modelsim AE/SE:

 

1) Move into the directory ./verilog/mentor or ./vhdl/mentor

2) Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".

 

 

After invoking the run.do command the simulation just runs. The reference clock and reset seem to be working fine (green), however, all the DDR3 memory signals remain undefined (red) and never change.

 

Please help.

 

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1 Reply
NurAida_A_Intel
Employee
72 Views

Hi Sir,

 

Thank you for joining this Intel Community.

 

May I know which Quartus release and the simulation tools version you are using?

Can you attach your IP top level file that can be opened by the IP parameter editor (or the .qsys file if the IP is instantiated in QSYS)? I’d like to check if the simulation example design works here.

 

Thanks

 

Regards,

Aida

 

 

 

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