FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5951 Discussions

Stratix V DDR3 simulation not working. All memory signals undefined.

SThom66
Beginner
391 Views

I ran the tcl command to generate the simulation files and then followed the instructions to run the simulation:

 

To generate the VHDL example design, open the Quartus project "generate_sim_example_design.qpf" and

select Tools -> Tcl Scripts... -> generate_sim_vhdl_example_design.tcl and click "Run".

Alternatively, you can run "quartus_sh -t generate_sim_vhdl_example_design.tcl"

at a Windows or Linux command prompt.

 

The generated files will be found in the subdirectory "vhdl".

 

To simulate the example design using Modelsim AE/SE:

 

1) Move into the directory ./verilog/mentor or ./vhdl/mentor

2) Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".

 

 

After invoking the run.do command the simulation just runs. The reference clock and reset seem to be working fine (green), however, all the DDR3 memory signals remain undefined (red) and never change.

 

Please help.

 

0 Kudos
2 Replies
NurAida_A_Intel
Employee
328 Views

Hi Sir,

 

Thank you for joining this Intel Community.

 

May I know which Quartus release and the simulation tools version you are using?

Can you attach your IP top level file that can be opened by the IP parameter editor (or the .qsys file if the IP is instantiated in QSYS)? I’d like to check if the simulation example design works here.

 

Thanks

 

Regards,

Aida

 

 

 

SimonRichter
New Contributor I
246 Views

Hi,

I have a similar issue with a simulated UniPHY based CycloneV DDR3 controller. I've tracked it down to the the CSR port on the DDR3 block, which isn't reset properly, so its csr_waitrequest, csr_rdata and csr_rdata_valid signals remain undefined.

The issue seems to be that the component instantiation_name_0002 (with "instantiation_name" replaced by the actual name) contains a signal csr_reset_n_ports_inv that is uninitialized and passed as the reset signal to the mm_interconnect_1 instance contained within it. It's obvious that this is an error, as that name exists only twice in the whole file, once as the signal definition and once where it is connected to an in port.

Inserting a line

csr_reset_n_ports_inv <= not csr_reset_n;

somewhere in the architecture body fixed this.

If the design connects both the CSR and the AVL ports to the same bus, this will make the entire bus appear as 'U' in simulation.

    Simon

 

Reply