Stratix4GX PCIe development board to used as root port

[Altera_Forum]

I wanted to know if anyone has used the Altera Stratix4GX PCIe card as  

a root port. I have used it as endpoint but have not used as a root-  port. As an endpoint all I have to do is plug in the card to a  motherboard. But as a root-port, it needs to send out the requests to  end point.

[Altera_Forum]

On the side to the Southbridge you will have to have a physical layer and you will have to do DLL stuff according to that link, i.e. flow control and buffering, low-level retransmission and so on. On the other side you have a link of different packet processing speed to the real or simulated CPU. If the model of the CPU includes everything down to DLL, you just have to add a (virtual) DLL on CPU side to your FPGA design with some simple packet exchange between these DLLs. It’s not desirable to simulate the physical layers of both CPU and the transparent FPGA bridge just to burn cycles.

[Altera_Forum]

I do not have the model for cpu side so initially I am thinking about using the PCIe BFM as root-port and end-point and inbetween them I use this pass through Transparent bridge. First step in doing this will require FPGA PCIe PHY model and synthesizable code. As per my understanding, in PCIe Gen1, I can just use PCIe Gen1 PHY on both side of this transapernt pass through bridge which vall pass all the packets on both sides. I will try to extract it out from already generated IP. Once I have simple pass through bridge working and simulated, I will slowly add components of DLL. I will need LCRC verilog module generator. I also need logic to figure out command boundary. If any of these can be leveraged then that will be great.

[Altera_Forum]

I don’t quite understand your first sentence. You probably meant “[…] so I thought about using the PCIe BFM as root-port and end-point […]”, as we worked out that this setup can not work as a bridge. 

 So for your task: You need two Gen1 PHYs, right. In between you have to build a bridge, but considering different rates, you have to build something for flow control as you might overrun your non-buffer badly. Remember that both interfaces run at their local clock rates, typically derived from the reception data rate.  You will have two simple DLLs on both sides maintaining the respective interface at its specific speed, writing TLPs at reception clock rate to the buffers and maintaining link-local flow control and other DLL tasks accordingly. You will have two uni-directional bridges for the two directions, reading TLPs at sender rate from the receiver’s buffer and outputting them on the sender side, straight through LCRC down to the PHY, whenever there are no other DLLPs to transfer. You will have to have clock domain crossing somewhere around the buffers.

[Altera_Forum]

At this point, I am trying to figure out what verilog modules I can leverage. I understand that I need the time domain translation logic for the speedbridge to work properly.  

 If I can get the following verilog modules then that can help expedite the development. If there are other major building blocks that can be leveraged then please let me know.    (1) Altera Stratix4GX PCIe PHY - This will be used on both sides for now in reality the emulator side may only pass TLPs and hence may not require PCIe PHY  (2) LCRC Verilog module for Data Link Layer. I understand that Data Link layer needs to pass DLLP packets and that will require additional custom logic.    I am thinking about creating this in a step by step manner.    As a first step I just put a transperent bridge that connects the two PHYs between the root-port BFM and the Altera endpoint.    I have been using the PCIe BFM as root port with Altera PCIe endpoint. I already have Altera PCIe endpoint simulatring with it. If I get the PCIe PHY module then I can connect them back to back. One side will be connected to the BFM and the other side to Altera endpoint. As per my understanding this can be done for Gen1 PCIe.   The next step will be to take the PHY output from each, make it look like TLP