FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

Synchronous multiple ports fifo

Altera_Forum
Honored Contributor II
1,433 Views

Hi All 

 

Is there any megafunction for multiple inputs and single output ports fifo based synchronized queue? OR Can anyone suggest other alternative ways? 

 

Thanks
0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
679 Views

No. That is something you will have to build yourself.

0 Kudos
Altera_Forum
Honored Contributor II
679 Views

Thanks for your reply. 

 

Can you help with this?  

 

I have one module with one input port. But input put for this module can come from multiple other modules. I should take the input FIFO basis. 

 

Thanks.
0 Kudos
Altera_Forum
Honored Contributor II
679 Views

Then you will need to work out some way to arbitrate between the sources. 

What rate are they all running at?
0 Kudos
Altera_Forum
Honored Contributor II
679 Views

usually 100MHz

0 Kudos
Reply