System console giving up when running the command "TEST_PHYSERIAL_LOOPBACK 0 1G 1000"

[Vamsi_21]

Hi,
I have generated the design example for Low latency ethernet 10g mac intel fpga ip-- 10M/100M/1G/10G example design(Arria 10) by following the below document.
https://www.intel.com/content/www/us/en/docs/programmable/683063/19-1-19-1/10m-100m-1g-10g-ethernet-design-example.html

While testing it on the hardware, I am getting the below error from system console.

“error: master_write_32: This transaction did not complete in 60 seconds. System console is giving up.
While executing
“master_write_32 sport_id $address $wdata”
(procedure “reg_write” line 7)
invoked from within
“reg_write $PHY_IP_BASE_ADDR $seq_control 0X111”
(procedure “SETPHY_SPEED_1G” line
invoked from within
“CONFIG_IPORT $speed_test”
(procedure “TEST_PHYSERIAL_LOOPBACK” line 10)
invoked from within
TEST_PHYSERIAL_LOOPBACK 0 1G 1000”

I have changed the USB blaster frequency to 16MHz,6MHz but still I am getting the issue.

Details:

Quartus used : Quartus prime 22.2
Board :Intel arria 10 GX development board
Device : 10AX115S2F45I1SG.

Below are the clock pin assignments
Name pin assigned
mm_clk 125Mhz BD24 clk_125
ref_clk_1g 125MHz N37 REFCLK_SMA (modified using clk controller).
ref_clk_10g 644.53125Mhz AA37 REFCLK_SFP

[ZiYing_Intel]

Hi Vamsi_21,

Could you try enable NPDME option and try testing again on hardware?

Best regards,

zying

[Vamsi_21]

Hi,

I have enabled NPDME option and generated the example design. 
I have given the pin assignments as follows
NAME                     pin assigned               
mm_clk                  BD24
ref_clk_10g           AN8 (modified using clock controller)
While testing on the hardware , i am getting the below error from system console.
error:TTK failed reading from PHY slave_2000, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset.
error: open_service: Could not open service at /devices/10AX115H(1|2|3|4|4E3)|..@1#2-13/(link)/JTAG/alt_sld_fab_0_alt_sld_fab_0_sldfabric.node_1/jtag_phy_0.jtag/master: Channel busy

while executing

"open_service master $port_id"
(procedure "reg_write" line 4)
invoked from within
"reg_write $PHY_IP_BASE_ADDR $seq_control 0x141"
(procedure "SETPHY_SPEED_10G" line
invoked from within
"SETPHY_SPEED_10G"
(procedure "CONFIG_1PORT" line 10)
invoked from within
"CONFIG_1PORT $speed_test"
(procedure "TEST_PHYSERIAL_LOOPBACK" line 10)
invoked from within
"TEST_PHYSERIAL_LOOPBACK 0 10G 1000"
Below i have attached the screenshot of the error.

[ZiYing_Intel]

Hi Vamsi_21,

Is there any update from you?

Best regards,

zying

[ZiYing_Intel]

Hi Vamsi_21,

For tranceiver phy, we don't use open service. You may refer link below https://community.intel.com/t5/FPGA-Wiki/Arria10-Transceiver-PHY-Basic-Design-Examples/ta-p/735196

There got a lot example designs inside the which may help you how to code in the system console.

Best regards,

zying

[Vamsi_21]

Hi,
I have checked for different jtag clock frequencies (24MHz, 16 MHz, 6MHz) and the reconfig_clk is assigned properly 
But in the system console iam  still getting the below error
error:"TTK failed reading from PHY slave_2000, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset."

[ZiYing_Intel]

Hi Vamsi_21,

Please check whether the reconfiguration clock is available according to the prompt information, and check whether the reconfiguration interface is in reset.

Best regards,

zying

[Vamsi_21]

Hi,
The design which i have generated is Low latency ethernet 10g mac intel fpga ip-- 10M/100M/1G/10G example design(Arria 10) by following the below document:
https://www.intel.com/content/www/us/en/docs/programmable/683063/19-1-19-1/10m-100m-1g-10g-ethernet-design-example.html

"In this design example i have generated , there is no reconfiguration clock and  no reconfiguration reset."
Below iam attaching the screenshot of the phy block from RTL viewer.

[ZiYing_Intel]

Hi Vamsi_21,

Could you try disable the NPDME option and try on hardware again?

Best regards,

zying

[Vamsi_21]

Hi,
I have disabled the NPDME option and tested on hardware, it is still showing the error below:
“error: master_write_32: This transaction did not complete in 60 seconds. System console is giving up.

While executing
“master_write_32 sport_id $address $wdata”
(procedure “reg_write” line 7)
invoked from within
“reg_write $PHY_IP_BASE_ADDR $seq_control 0X111”
(procedure “SETPHY_SPEED_1G” line
invoked from within
“CONFIG_IPORT $speed_test”
(procedure “TEST_PHYSERIAL_LOOPBACK” line 10)
invoked from within
TEST_PHYSERIAL_LOOPBACK 0 1G 1000”.

[ZiYing_Intel]

Hi Vamsi_21,

It seems like need the enable the NPDME options. We can narrow down the issue first. Give me some time to find out the possibility that can make the TTK fail reading fail occur. In the meantime, you also can check the connection.

[ZiYing_Intel]

Hi Vamsi_21,

I just get to know that the EyeQ is no longer supported in A10 devices. It seems to be due to some issue with the EyeQ result. Please avoid using the EyeQ. Do you use the EyeQ?

Best regards,

zying

[Vamsi_21]

Hi, I am not using EyeQ, 
I am using signal tap logic analyzer tool.

[ZiYing_Intel]

Hi Vamsi_21,

Can you share your .qar file? So that I can try debug the issue from my side.

Best regards,

zying

[Vamsi_21]

Hi,                                                                                                                                                                                                                                                        Below I am sharing the .qar file 

[ZiYing_Intel]

Hi Vamsi_21,

Can we try connect the reconfiguration clock and reconfiguration reset ?

Best regards,

zying

[Vamsi_21]

Hi,                                                                                                                                                                                                                                                        In the example design which i generated there is no reconfiguration clock and reconfiguration reset.                                                                     Below i am sharing the screenshot of phy from RTL viewer.

[ZiYing_Intel]

Hi Vamsi_21,

I don't found any .tcl file inside the .qar file that your share? Please share the .qar file with the .tcl file inside it. So that I can debug the same issue from my side.

Best regards,

zying

[Vamsi_21]

Hi,
I have added the .tcl file and I am sharing the .qar file

[ZiYing_Intel]

Hi Vamsi_21,

Can you try using another Quartus Prime Pro version 22.3? I don't see the error on Quartus 22.3 but I am using different opn.

Best regards,

zying

[Vamsi_21]

Hi, 
I have tried with Quartus Prime Pro version 22.2 , can u try with the same version of Quartus prime pro version.