TSE FIFO buffer for multiple packets

[Konrad-Techtest]

I am using the TSE to receive a small number Ethernet packets that arrive back to back (i.e. with the minimum inter-frame gap). 

   (100Mbps, 64byte to 512Byte payloads, UDP, 16 packets bunched...repeated every 100mS)

This is a closed system, no other packets, no auto-negotiation etc.

I have my own Avalon-ST interface that reads in-coming packets into another VHDL module.  This all works, but, my own code only buffers a single packet at a time, and I am dropping packets.

If I set the TSE FIFO Rx buffer to 8K, can I then use the Avalon-ST Ready signal to make use of the internal FIFO buffer.  That is, use back pressure to slow down my reads.

Does the TSE continue to receive multiple packets into the FIFO when the Avalon-ST Ready signal is low?

I was looking at creating my own packet wide FIFO buffer post Avalon-ST reception, but this is looking more complicated for me.

[Deshi_Intel]

HI,

Typical FIFO design should contains its own threshold setting like full or empty to prevent overflow or underflow situation. (aka back pressure flow control)

If you are using TSE IP internal FIFO then it contains even more threshold control mechanism as shown in chapter 4.1.6. FIFO Buffer Thresholds (page 46).

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf
• Pls check out the TSE user guide chapter 4.1.6 for more detail

Thanks.

Regards,

dlim