FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6425 Discussions

missing design example from design store

Rk_Athram
New Contributor I
342 Views

Hi I am trying to implement manual DFE parameters using RTL,

for reference design i have gone through below link 

https://community.intel.com/t5/FPGA-Wiki/Arria10-Transceiver-PHY-Basic-Design-Examples/ta-p/735196

 

but 

Arria 10 Native PHY design example showing converged DFE tap values reading steps

 

the link is broken, please share the downloadable link .

0 Kudos
2 Replies
CheePin_C_Intel
Employee
328 Views

Hi,

As I understand it, you are looking for a A10 example design on reading the DFE tap previously from wiki. For your information, I am not sure why the link is broken. However, I am attaching a local copy which I previously download from wiki for your reference to see if it is helpful.

Please let me know if there is nay concern. Thank you.

0 Kudos
CheePin_C_Intel
Employee
314 Views

Hi,


I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


0 Kudos
Reply