FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

TSE PHY Loopback

Honored Contributor II

Hi everyone, 


We are using Arria V GX FPGA, and the IP Core TSE 1000Base-X/SGMII with PCS and PMA. I am trying to activate the PHY loopback but couldn’t get it to work as it’s my first time to work with Ethernet. 

The sequence is as follows: 


  1. Write to PCS Control register 0x00 : “0100000101100000”  


So I enable the Uniderectional option to be able to send data without a link partner 

Activate gigabit mode 

Activate loopback mode 



  1. If_Mode register 0x14 : "0000000000001001"  


SGMII_ENA set to 1, USE_SGMII_AN set to 0, SGMII_SPEED to gigabit mode 



  1. Then I reset the PCS by setting bit 15 of control register to 1  



Can I afterwards start to write data by setting the gmii_tx_clk_en to 1 and writing a byte to gmii_tx_d without having a valid link? Or I still need to do something because currently I don’t see any data on rx. I also read the PCS registers and confirmed that they were correctly written.  


Thanks in advance.
0 Kudos
0 Replies