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Altera_Forum
Honored Contributor I
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TSE and auto generated .sdc

I'm not really understanding how to correctly use the auto generated .sdc file to constrain the TSE. I have two clocks coming in at 25 MHz, as I am only using the 100 Mb configuration 

 

create_clock -name {enet_rx_clk} -period "25MHz" create_clock -name {enet_tx_clk} -period "25MHz" I also have a system clk at 80 MHz, called sys_clk. I'm not sure as to how these three clocks figure in to the following section from the user manual. 

 

Edit <variation_name>_constraints.tcl and <variation_name>_constraints.sdc 

according to your customized design. For example, if you change the clock names 

at the top-level design, edit the customer modifiable constraints in the 

<variation_name>_constraints.sdc file to change the clock names shown below:# Name the clocks that will be coming into the tse core named 

changed from top level 

set TX_CLK "tx_clk" 

set RX_CLK "rx_clk" 

set CLK "clk" 

set FF_TX_CLK "ff_tx_clk" 

set FF_RX_CLK "ff_rx_clk" 

set TBI_TX_CLK "tbi_tx_clk" 

set TBI_RX_CLK "tbi_rx_clk" 

set REF_CLK "ref_clk" 

 

Should I be using this auto generated file at all, or should I just make my own constraints?
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