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Valued Contributor III

Timing Adapter - ready latency



In our SOPC system we have a timing adapter between two units. 

The Avalon streaming bus has a 32 bits data bus and uses start of packet, end of packet and ready handshaking. 


The Avalon ST Source has a ready latency of 0, the Avalon ST Sink has a ready latency of 1. The timing adapter should fix this mismatch. This is what I see on the Avalonk Sink port: 


When the Avalon Sink deasserts its ready after an end of packet, the valid signal on the Avalon Sink is also deasserted, as expected. However, during the non-ready period there is a Start of Packet with data. So ready and valid are still deasserted, but the Start of packet and data is driven for one clock period, after that the behavour is as expected ... 


Does somebody recognize this erroneous assertion of Start of Packet and data? 


Thank you in advance, 

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Valued Contributor III



Today I read in the manual of the TSE this: 


The ready latency of the MAC Receive interface is two when internal fifo's are used, but the latency is reduced to 0 when the TSE is used in SOPC by means of a timing adapter. 


Is the timing adapter automatically inserted, and so part of the TSE SOPC Component, or do they mean that I have to add a timing adapter. In simulation I can see the ready latency of 2 at the TSE interface. So, i changed my timing adapter from 0 -> 1 to 2 -> 1 ..... with succes. 


Can someone confirm that: 


1) the TSE SOPC component itself has a ready latency of 2 at its RX MAC i/f 

2) i need to add the timing adapter and make a match between the TSE with RL=2 and my own component with a RL of 1? 


Thanks in advance, 

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