Hello,I'm testing out the DDR2 high performance controller II, but when compiling the example design, the timing requirements are not met. The critical path is through a PLL deep in the megafunction. I get a warning about this PLL, saying its second output clock is not connected: Warning: PLL "ddr2_cntrl_example_top:example_inst|ddr2_cntrl:ddr2_cntrl_inst|ddr2_cntrl_controller_phy:ddr2_cntrl_controller_phy_inst|ddr2_cntrl_phy:ddr2_cntrl_phy_inst|ddr2_cntrl_phy_alt_mem_phy:ddr2_cntrl_phy_alt_mem_phy_inst|ddr2_cntrl_phy_alt_mem_phy_clk_reset:clk|ddr2_cntrl_phy_alt_mem_phy_pll:full_rate.pll|altpll:altpll_component|altpll_aqr3:auto_generated|pll1" has parameters clk2_multiply_by and clk2_divide_by specified but port CLK is not connected) The critical path's clock is the first clock of this PLL. Anyone else got this issue? I'm using Quartus 10.0 SP1.
Some more information about the problem:Timing is violated in the Phy part of the controller. It is the setup time that is violated. The clock source is the auto-generated PLL mentioned above. Megafunction parameters: Device familiy: Arria II GX Speed grade: 4 PLL reference clock freq: 100 MHz Memory clock frequency : 333.333 MHz Controller data rate: full, with half rate bridge enabled Memory preset: Micron MT8HTF12864HY-800 @ 333 MHz Using differential DQS Address/command clock phase: 90 degrees Board settings: default altera settings, with 1 slot Controller settings: High performance controller II Rest here is default I'm using the Arria II GX development kit. All signals to/from the SODIMM are placed on the bottom I/O banks, as well as the 100MHz clock source. Any help would be greatly appreciated :-)
I searched a bit deeper in the documentation and found the 333 MHz performance for the Arria II GX in half-rate mode. However, you selected a full-rate controller with a half rate bridge enabled. I have no idea whether this is interpreted as 'full' or as 'half'. Maybe you better select plain 'half' rate controller.
Thank you, the timing is closed using half-rate, but I also had to reduce the memory frequency to 200 MHz. I also found out my device is speed grade 5 :PHowever, when running the example_top design on the hardware, the test_complete signal stays deasserted. I would think this is due to some board timing specifications, but I cannot find any such specifications in the documentation that came with the kit (Arria II GX dev kit). Do you know where I could find these? That would've been awesome :). Also, do you know what the pnf and pnf_per_byte signals in the example top is? I should probably do some signal-tapping... :)
PassNotFail, I remembered.I am not that familiar with the Arria II GX devkit, actually I almost never use devkits. (unless to learn from the schematic ...) According to the documentation the C5 speed grade can handle a 333 MHz half rate design but with a 400MHz DDR2 device.
OK, thanks again!The example design seems to run okay at 300MHz as well, although TimeQuest still reported some timing issues.. It might be best to run it slower to be absolutely sure. But the PNF signal stays asserted all the time. No wonder why the test_complete led never lights, because this is only a pulse between the read/write tests. Not using dev kits: respect! :-)