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Altera_Forum

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06-13-2016
02:32 PM

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Trouble with CIC filter

I'm trying to implement a CIC decimation filter( with R = 1000, M = 1 and N = 2 ) and Fs = 1 MHz without using the CIC IP core. Using matlab implementation I found out that the suppression of the CIC filter will be 26.58 dB for all frequencies above 500Hz which is relatively good for my project. But on implementing the CIC filter whenever I'm passing a signal of 1KHz, the output of the cic filter is a dc offset which is the expected result but on passing frequencies above 5KHz I'm getting output of the CIC filter as noise. Can anyone please help me finding what's wrong with the code. The attachment contains the matlab freq response.

The data input is 12 bit, so the output will be 32 bit as per the CIC filter register growth equation. ENTITY cic_filter IS PORT( clk_in : IN std_logic; -- input sample rate clock(1 MHz) data_in : IN std_logic_vector(11 downto 0); -- sample data in, Q12._ clk_out : OUT std_logic; -- output clock (clk_in / 1000) data_out : OUT std_logic_vector(31 downto 0) -- data out ); END cic_filter; ARCHITECTURE behavior OF cic_filter IS -- latched, 32-bit data in signal l_data_in : signed(31 downto 0); -- outputs for each integrator stage signal integrator_out_1, integrator_out_2 : signed(31 downto 0) := (others => '0'); -- delayed outputs for each integrator stage signal l_integrator_out_1, l_integrator_out_2 : signed(31 downto 0) := (others => '0'); -- inputs for each comb stage signal comb_in_1, comb_in_2 : signed(31 downto 0) := (others => '0'); -- delayed inputs for each comb stage signal l_comb_in_1, l_comb_in_2 : signed(31 downto 0) := (others => '0'); -- decimation clock signal clk_decimated : std_logic; signal count : natural range 1 to 1000 := 1; begin l_data_in <= resize(signed(data_in),32); integrators : process( clk_in ) begin if( rising_edge(clk_in) ) then -- sums integrator_out_1 <= (l_data_in) + l_integrator_out_1; integrator_out_2 <= integrator_out_1 + l_integrator_out_2; -- delays l_integrator_out_1 <= integrator_out_1; l_integrator_out_2 <= integrator_out_2; end if; end process; decimation_clock : process( clk_in ) begin if( rising_edge(clk_in) ) then if( count = 1000 ) then count <= 1; clk_decimated <= '1'; else count <= count + 1; clk_decimated <= '0'; end if; end if; end process decimation_clock; clk_out <= clk_decimated; combs : process( clk_decimated ) begin if( rising_edge(clk_decimated) ) then -- decimation of integrator output comb_in_1 <= integrator_out_2; -- sums comb_in_2 <= comb_in_1 - l_comb_in_1; data_out <= std_logic_vector( comb_in_2 - l_comb_in_2 ); -- delays l_comb_in_1 <= comb_in_1; l_comb_in_2 <= comb_in_2; end if; end process; end behavior;Link Copied

11 Replies

Altera_Forum

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06-13-2016
02:56 PM

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without diving too deep you are implementing M as 2 as you are delaying extra:

I believe below is for M = 1 integrator_out_1 <= (l_data_in) +integrator_out_1; i.e. just acccumulator
Altera_Forum

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06-13-2016
03:21 PM

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Hi Kaz,

Could you please be more elaborate ? I'm not able to get you. M - differential delay which I'm setting equal to 1, and N is the number of stages which is 2 is my case.
Altera_Forum

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06-13-2016
03:26 PM

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Altera_Forum

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06-13-2016
03:35 PM

46 Views

So that means I don't need the

-- delays l_integrator_out_1 <= integrator_out_1; l_integrator_out_2 <= integrator_out_2; rather I only need integrator_out_1 <= (l_data_in) + integrator_out_1; -- ( o/p of the 1st integrator ) integrator_out_2 <= integrator_out_1 + integrator_out_2; -- (o/p of the 2nd integrator feed into the input of a comb)
Altera_Forum

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06-13-2016
03:40 PM

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Altera_Forum

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06-13-2016
03:48 PM

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Thanks for the information. So for the comb similar will be the case right ?

comb_in_2 <= comb_in_1 - comb_in_1; data_out <= std_logic_vector( comb_in_2 - comb_in_2 ); Let me try this
Altera_Forum

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06-13-2016
03:51 PM

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Altera_Forum

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06-13-2016
04:02 PM

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Yup.. what was I thinking. Then for the comb I need to use the delay element right ?

Altera_Forum

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06-13-2016
04:17 PM

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Still I'm getting noise at the output when passing 5 KHz signal, can't figure out why

Altera_Forum

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06-13-2016
07:45 PM

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Thanks a lot for your input. It worked :)

Altera_Forum

Honored Contributor I

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06-14-2016
02:43 PM

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Hi Kaz,

I have one more issue : I'm using a FIFO IP with width of the fifo being 16 bit and the depth of the fifo buffer is 16384 words. I'm using the MAX10 development kit and interfacing it with Matlab. The baud rate is set to 115200 bps. Data is being written in the fifo buffer continuously and when I send read command from matlab, data is being read from the fifo buffer. It happens sometimes that the fifo buffer is getting emptied at a faster rate than data being written into it and my matlab program terminates. Can anyone please help me with this issue. ThanksFor more complete information about compiler optimizations, see our Optimization Notice.