FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5741 Discussions

Turbo IP Core Tail/Trellis Termination

jwplex
Beginner
223 Views

The user guide (https://www.intel.com/content/www/us/en/programmable/documentation/dmi1436868893828.html) for the Turbo IP core does not list any information about tail/trellis termination bits. When I simulate the encoder I get a 3-value tuple for 4 cycles at the end of encoded frame, which corresponds to the expected 12 tail bits. However, I would normally expect this to be a 4-tuple (systematic tail, parity tail, interleaved systematic tail, interleaved parity tail) for 3 cycles to get 12 tail bits. There is no description in the user guide as to how the 4-tuple is multiplexed onto 3 outputs for 4 cycles. I'm currently assuming the automagically come out in the correct order if I serialize them from 0 to 2 for over 12 cycles. I can't verify this to be true though, as the tail bits generated by this core (encoder) only match for 3 of the 4 tuples against several MATLAB 3GPP encoders.

0 Kudos
4 Replies
CheePin_C_Intel
Employee
217 Views

Hi,


As I understand it, you have some inquiries related to the Turbo IP. The specific information seems not available in the user guide. Please allow me some time to further look into this and consult Factory if necessary. I will keep you posted on the progress by end of next week. Please ping me if you do not hear back from me. Thank you very much.


CheePin_C_Intel
Employee
210 Views

Hi,


Just to keep you posted on the progress. For your information, I am unable to locate any specific info on the tail bits in the documentation or internal database. I am currently consulting peers to see if they might have any insight on this.


By the way, just would like to check with you if you are observing any issue with the encoded data ie decoder is unable to recover the initial data fed into encoder.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin



CheePin_C_Intel
Employee
210 Views

Hi,


As I understand it, you are observing this in simulation. Would you mind to share with us some screenshots to that we are on the same page? 


Just would like to check with you also if you are observing this with the IP generated example design?


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin



CheePin_C_Intel
Employee
202 Views

Hi,


For your information, per my discussion with peers, seems like there is no specific information on the trellis termination. We believe that this is something internal to the IP and thus there is no specific info available in the user guide. Just to check with you if you are observing any incorrect behavior from the IP?


By the way, we found an AN which is discussing about the 3GPP LTE Turbo Reference Design (https://www.intel.co.jp/content/dam/www/programmable/us/en/pdfs/literature/an/an505.pdf). Note that this LTE Turbo is different from the Turbo IP that is available from the IP Catalog Editor. There is some Trellis termination info in the AN. Since I am not really a design specialist, I do not have much insight on the Trellis termination. Probably you can take a look to see if it is something helpful. 


Please let me know if there is any concern. Thank you.


Reply