Two HBM2 instances with single I/O PLL

[MichaelB]

Hello!

Currently I'm evaluating the Intel Stratix 10 MX.

I'd like to know if it's possible to drive the top & bottom HBM2 with a single I/O PLL.

I already tried to set up the system but I've recognised I cannot wire the PLL_LOCKED signal to both instances.

• Is this even possible to drive both HBM2 with a single I/O PLL?
• Are there any negative impacts I could face using a single I/O PLL?

Best regards,

Michael

[NurAida_A_Intel]

Dear Michael,

Thank you for joining this Intel Community.

I would like to confirm again with you to make sure we are on the same page.

May I know which IOPLL you are referring to here?

Is it the IOPLL insides HBM2 IP ? Or you are referring to IOPLL for your own user logic design that interact with both HBM2 IP? Please help to confirm.

Thanks

Regards,

Aida

[MichaelB]

Dear Aida,

thanks for your reply!

I'm referring to the IOPLL for my own user logic which has to be instantiated by myself (not the PLL inside of HBM2).

Thank you and best regards,

Michael

[NurAida_A_Intel · Accepted solution]

Hi Michael,

Thanks for the confirmation.

If IOPLL from own user logic, you may share it as long it provides your design fits and closes timing.

The drawback of resource sharing is always problem with design timing closure because you need to use same PLL to clock too many destinations in the design. Once the clock signal travel too far, it will become jittery and impact the timing. That is why sharing resources is not a recommendation.

But, you can evaluate your design using Timequest and see is there any timing closure impact or not. If everything is fine, then I don’t see any problem sharing the IOPLL.

Hope this explanation helps. 😊

Thanks

Regards,

Aida

[MichaelB]

Due I want to run HBM2 with maximum frequency I'll instantiated a main (upstream) IOPLL with two sub (downstream) IOPLLs to achieve best timing closure.

Thanks a lot for your explanation! 🙂