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Hi all,
I am running a project that requires high data bandwidth with external memory. Moreover, READ/WRITE ratio is nearly 1:1 and I'm looking for a very low-cost solution. I thus tried to implement two 16-bit wide DDR2 hp controllers (one for reading and one for writing simultaneously) on a small EP3C10F256C8. Modelsim-simulation and synthesis run well. But Fitter definitely fails with the following error : "Following nodes require the same Clock control Block" (one from the second controller and my main clock input). If I choose a larger FPGA (EP3C16), everything works. However, following the compilation report summary, the EP3C10 should be enough. Is it possible to assign the Clock control Block manually ? Or is it another solution to fit my EP3C10 ? Thanks in advance JlCLink Copied
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