FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 Discussions

UART IP make SOPC Builder starting slow?

Altera_Forum
Honored Contributor II
1,142 Views

I am trying to add the fifoed uart IP (cal uart) into my project, but i find the SOPC Builder started very slow. 21 uarts are used in my project and it needs more than 30 minites to start the SOPC Builder. it pauseed at "open system" window. Does anybody meet the problem, or anyone know how to resolve it. thanks very much.

0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
430 Views

what version of Quartus II are you using? there was a bug in versions previous to 10.1 that caused slowness when using certain components such as the FIFOed UART. this is supposed to be fixed in 10.1, i haven't verified

0 Kudos
Altera_Forum
Honored Contributor II
430 Views

Thanks. I am using Quartus II 9.1.

0 Kudos
Reply