05-31-2019 01:40 PM
I'm getting this error when trying to debug my Stratix IV GX board in Quartus 18.1.
This error is the same as this old post, but the solution proposed isn't working in 18.1.
06-04-2019 02:08 AM
Hi, Can you check whether you had provided clock to pll_refclk pin and release the global_reset pin ? Thanks. Is this issue occurs on Intel FPGA dev kit board or your own board ? Regards, Deshi
06-11-2019 03:33 PM
06-12-2019 10:54 AM
Hi, global_reset_n pin is the control signal for EMIF IP reset function. What I am saying is have you release EMIF IP from reset stage by setting global_reset_n pin to high ? The other thing that I suspect is how many EMIF IP interfaces that you have in your design ? It's recommend to have EMIF toolkit to interact with one EMIF IP interface only. So, you can try to reduce your design complexity till having one EMIF toolkit to interact with one EMIF IP and nothing else in your Quartus design. Another thing is EMIF toolkit is relying on JTAG connection to interact with EMIF IP. "Device has different visible SLD agents" error seems to indicate there are multiple JTAG connection in either your board or in Quartus design that confuse the EMIF toolkit. Thanks. Regards, dlim