Uniphy DDR3 Data Corruption

[Fletch]

I'm hoping someone in this forum has some insight on data corruption I am seeing when accessing a discrete DDR3 using Uniphy IP.

I first noticed data errors when using it as a video frame buffer. Now, I am observing these errors with the Uniphy connected to the Avalon-MM Traffic Generator and BIST Engine. I'm only performing sequential accesses, which makes it easy to pinpoint where failures begin. The data remains accurate for a short period before errors start to appear. These errors consistently occur early in the test, but not at the same point each time. Once the accesses start to fail, data errors persist throughout the rest of the test. I have attached a SignalTap capture that shows this behavior. The errors start to appear after a longer period where the avl_ready signal is low. Could this be related to a DDR refresh?

The part number of the the DDR3 we are using is MT41K256M16TW-107IT.  We are using legacy 1.5V and A14 is not connected (it’s pulled to ground through a 10Kohm), so the timing is a little confusing. There are presets for MT41J128M16 which agrees with this device since A14 is not used. I’ve also tried the timing for the MT41J256M16 with the row address reduced by 1. Both cases behave the same. The memory interface is being accessed at 300MHz.

I saw a post on here about 1.5v ripple causing data corruption, but the ripple on our board is only 50mV.

It has never failed calibration and looks to have a lot of margin, see attached report. Also, the timing is closed.

Quartus Prime Lite 23.1std.0 Build 991

Cyclone V: 5CGXFC7D6F27I7

Thanks for any insight.  

[Andrey4]

Hello! I'm also using two chips "MT41K256M16DA-107" as a video frame buffer. Avalon-MM interface is 128-bit data and 26-bit address. I fill the frame with some test data. I looked in Signal Tap, and it shows that data from some memory address cells is not the same as I wrote before (see attached file - each address should contain 0xf800f800f800f80007e007e007e007e0, but some of them suddenly contain something else). And I have some artifacts on display because of this

[AdzimZM_Intel]

Hello Fletch,

Is this design running in the generated DDR3 example design?

Can you run the DDR3 at 303MHz?

Have tested with some difference burst length value for Traffic Generator setup and UniPHY IP setup?

Regards,

Adzim

[Fletch · Accepted solution]

Hi Adzim,

I was able to correct this. My refresh cycle time was too short.

Thanks,

Brandon