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Using Parallel Flash Loader IP without JTAG

MFric2
Beginner
1,246 Views

Hello,

 

we are using the Parallel Flash Loader IP Core with a MAX II to Programm a Flash Memory and Configure an Cyclone V E FPGA.

 

This works fine so far with Programming the Flash over Quartus Programmer with USB Blaster and JTAG.

 

What we try do is:

 

We plan to programm the flash in production over an external host (e.g. another FPGA) that transfers bitstream data over SPI to the MAX II device.

 

The MAX II which holds the PFL IP Core should act as SPI Slave device and programm the Flash memory with the data he gets from the SPI Master.

 

Did someone already done this ?

Or is it possible to tell the PFL IP to take the data from SPI ?

Maybe its a better solution to programm the flash memory directly with logic in MAX II and do not use PFL IP ?

 

Has anyone ever had experience in this area?

 

Thanks !!!

 

 

0 Kudos
1 Reply
Nooraini_Y_Intel
Employee
152 Views

Hi MFric2,

 

Perhaps you may consider to use NIOS II with Avalon Tri-State Conduit components in FPGA to access the CFI flash. The PFL can only be use with Quartus programmer via JTAG interface. You can refer to chapter 5.2.6. Nios II Processor Booting from CFI Flash in the Embedded Design handbook for the details:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pd...

 

We don't have the exact method that you are looking but you can try refer to the Cyclone V dev kit which has similar application. Please refer to the link below for the Cyclone V dev kit reference manual, schematic and BUP(board portal update) design as reference:

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cy...

 

Most of the FPGA dev kit come with the BUP(board portal update) design that utilize NIOS II with Avalon Tri-State Conduit components in FPGA. While the PFL in CPLD is use to perform the FPPx16 configuration to Cyclone V.

 

You can refer to chapter "FPGA Programming from Flash Memory" for some explanation and Figure 2–4. PFL Configuration on the FPGA-CPLD-flash connection from the Cyclone V GT dev kit reference manual:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/rm_cvgt_fpga_dev_boa...

 

Regards,

Nooraini

 

 

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