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Altera_Forum
Honored Contributor I
889 Views

Using SODIMM DDR2 module on Cyclone 3

Hi All, 

 

Hope someone can help. 

 

I'm just trying to establish the feasibility of using a SODIMM memory DDR2 memory module (e.g Micron MT16HTS25664H) with a Cyclone III FPGA (EP3C40F484C6 or 7). This is the 2Gbyte part, though we could potentially want to use the 4Gbyte part. 

 

We currently have a Cyclone 2 FPGA on the board as it stands, with a 32Mbyte DDR memory chip (not module) which works very well. However we need to expand the memory capabilities and memory modules seem to offer substantial cost savings. 

 

I'm concerned that the memory bus width of the SODIMM module is 64bits and the documentation seems to imply that this would not be supported by the Cyclone 3 and the DDR2 controller block from Altera. 

 

Does anyone have experience of driving SODIMM modules using a Cyclone 3? 

 

many thanks 

Richard.
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11 Replies
Altera_Forum
Honored Contributor I
67 Views

I've used SODIMM with Arria, but I understand from the IP manual, that Cyclone III DDR2 interface with 64 data lines (8x8) can be realized. I'm not sure, if it's possible with the F484 package. The most simple way to find out is starting a test design, I think.

Altera_Forum
Honored Contributor I
67 Views

You would need 8 x8 DQS groups, which can be supported on the 40F484, (C3 device handbook, table 9-5) but it will take all the IO banks on the two sides of the chip just for DQ groups. The address/command will be on a third side. 

 

So it should fit, but your problem is that it will use the majority of the pins on your chip, and many of the remainder will be forced to a 1.8v IO standard. 

 

The problem is likely to be running out of pins or IO banks to do other useful stuff with, but a quick IO ring design should clear that up. 

 

Another resource to keep an eye on is clocks and clock networks. The rules are compicated and varied so FvM's suggestion of a test design is a good idea if you can.
Altera_Forum
Honored Contributor I
67 Views

It may be worthwile to look whether you need the full speed, if not you could implement the memory interface using a PLL to clock the SDRAM read data. This will allow you to optimize the pin per bank usage.

Altera_Forum
Honored Contributor I
67 Views

josyb: I'd recommend against trying to build a DDR2 memory interface from scratch: it is a big project.

Altera_Forum
Honored Contributor I
67 Views

The PLL-feedback was supported in earlier versions of Quartus and for CycloneII and StratixII. I just checked the MegaWizard and for CycloneIII Altera chose to 'only' deliver the 'advanced' solution (ALTMEMPHY ...). But you're right, doing the PLL approach from scratch will be a big project. 

The EP3C40F484 has 16 DQSx8 groups, so rws28 should be able to implement his DIMM interface just using 2 sides, because, to my idea, he can use the non-DQ pins to supply command and address to the DIMM. That would leave the 2 other sides for interfacing logic with a different VccIO voltage.
Altera_Forum
Honored Contributor I
67 Views

I am also interested in using a 4GB sodimm w/ the CycloneIII except I will be using the largest CycloneIII EP3C120. When trying to add the hpddr2 controller in sopc builder I get the following errors: 

 

Error: cpu_0: Nios II Instruction Master cannot address memories over 2^32 

Error: cpu_0: Nios II Data Master cannot address memories over 2^32 

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits 

 

 

Does this mean that 4GB is not supported? When changing it to a 2GB I part I still get this error: 

 

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits 

 

Only when I change to a 1GB do the errors go away. I really need to use the 4GB sodimm, is there any way around this problem? 

 

Thank you! 

Brianna
Altera_Forum
Honored Contributor I
67 Views

I guess you could build a bridge that would map some part of the DDR address space into the 31 bits that the Nios can access. Permanently map the bottom 512Mb of the address space to the bottom of the DDR memory, then have a few control bits to select which 512Mb page of the DDR is available in the top half.

Altera_Forum
Honored Contributor I
67 Views

 

--- Quote Start ---  

I am also interested in using a 4GB sodimm w/ the CycloneIII except I will be using the largest CycloneIII EP3C120. When trying to add the hpddr2 controller in sopc builder I get the following errors: 

 

Error: cpu_0: Nios II Instruction Master cannot address memories over 2^32 

Error: cpu_0: Nios II Data Master cannot address memories over 2^32 

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits 

 

 

Does this mean that 4GB is not supported? When changing it to a 2GB I part I still get this error: 

 

Error: cpu_0: Memory map cannot fit within the addressable memory space of the Nios II Data Master which is restricted to 31 address bits 

 

Only when I change to a 1GB do the errors go away. I really need to use the 4GB sodimm, is there any way around this problem? 

 

Thank you! 

Brianna 

--- Quote End ---  

 

 

These errors are a limitation of the NIOS CPU, not the DDR core. As Phil Wise suggested, an intermediate module with a page register would solve the addressing errors. 

 

The big problem is going to be fitting the controller so it meets timing with the DQ groups placed on opposite sides of the chip(this can be more difficult with a larger FPGA). I know for Stratix and Arria, Altera recommends that the DQ groups be placed on one side or one corner of the chip - this probably applies to Cyclone devices too. As you can see from http://www.altera.com/literature/hb/cyc3/cyc3_ciii51008.pdf, none of the Cyclone III packages offer more than 6 x8 groups per side. 

 

It would be best to instantiate a 4 GB memory controller separately at the speed you want (with the Megawizard, not SOPC builder), create a simple pass-through Avalon interface to the NIOS (just chop off the top bits; paging can be implemented later), pin it out, and run a timing analysis. If it doesn't meet timing, turn on all the fitter optimizations and turn of the placement/fitter effort. If it still doesn't meet timing at the lowest speed that meets your design requirements, you might be out of luck.
Altera_Forum
Honored Contributor I
67 Views

Can i use SODIMM DDR2 module on ep3c16f484?

Altera_Forum
Honored Contributor I
67 Views

The question has been answered positively in the thread. There are different opinions, how many IO banks must be occupied with 1V8 VCCIO.

Altera_Forum
Honored Contributor I
67 Views

I encountered the same problem. In Cyclone4 devices, only 1 side cannot support a DIMM with 200 pins. If we use DIMM in cyclone series, 2 sides at least should be used. It's harder to achieve higher frequency when using 2 sides, but 167MHz could be guarrented.

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