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Problems with the CVI and CVO Sof-Signals

Honored Contributor II



I really need help. I have a simple VideoProcessing Modul. I hav a CVI --> ChromaResampler --> CVO, and a Cylone IV E 


I have different clocks for the PixelClock-Input an the PixelClock Output. Both are 74.25MHz but the Input PixelClock is an external Clock, and the Output-Pixel_Clock is an PLL-generatet Pixel-Clock. I need this PLL - Clock because the other clock has Jitter/Wander on it. 


I don't have a NIOS in my System. I connected the sof_input and the sof_input_locked Signal with the output_sof_locked and the outpu_sof-Signal. 


I changed some lines in the control-vhdl-Code in the IP-File. 

In this File "alt_vipcti120_Vid2IS_control" I changed  

Line 143 assign enable = 1'b1; 

Line 113 - 121 

genlock_enable <= 1'b1; 

interrupt_enable <= 2'b00; 

enable_reg <= 1'b1; 

status_update_int_reg <= 1'b0; 

stable_int_reg <= 1'b0; 

sof_sample <= 14'd2194; 

sof_subsample <= 2'd1; 

sof_line <= 13'd1124; 

refclk_divider_value <= 14'd1; 


On the CVO File "alt_vipitc120_IS2Vid_control" 

I changed Line 94 - 99 

if (rst) begin 

genlock_enable_reg <= 2'b1; 

interrupt_enable <= 2'b1; 

enable_reg <= 1'b1; 

status_update_int_reg <= 1'b0; 

genlocked_int_reg <= 1'b0; 

and Line 117 

assign enable = 1'b1; 


This works for about 3 Minutes, in this Time I can see a stable picture, but then I get an CVI-FIFO Overflow and my analyzer can still detect the right Videoformat, but I only get a black picture. After a few Minutes the picture startet to change the colour. 

If I use my Video-Input_pixel-Clock as my VideoOutput_Pixel-Clock I alwys get a stable picture. 


Please tell me, what can I do against this overflow? What can I do to synchonize the Input and the Output without the same Pixel_clock. 


Can anybody help me? 


Thanx Anja
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