FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

VHDL Use Clause Error

Altera_Forum
Honored Contributor II
1,409 Views

Hi, 

When I try to compile in Signal Compiler I get the error: 

 

"Error (10481): VHDL Use Clause error at FIRFilter_FIRSubBlock2_AddSubsystem.vhd(28): design library "fpc" does not contain primary unit "hcc_package" File:" 

 

I saw here, http://www.altera.com/support/kdb/solutions/rd07222003_3973.html

that a VHDL Use Clause Error can occur if I compile a DSPBuilder project from quartus, but this error should not occur when compiling from signal compiler. 

 

Any help would be greatly appreciated. 

 

Thank You, 

rushale
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
582 Views

To anyone facing a similar error, I solved this problem by going to Add/Remove Files in Project... under the Project menu in Quartus II and adding all of the files in the folder D:\altera\11.0\quartus\dspba\libraries\vhdl\fpc. The files include hcc_package.vhd, math_package.vhd, and fpc_library_package.vhd. 

 

If anyone knows how to avoid manually adding library files I would appreciate your advice. 

Kind Regards, 

rushale
0 Kudos
Altera_Forum
Honored Contributor II
582 Views

I think this should do what you want. (Steps 3+4 are required to make modelsim testbenches work as well). 

 

1. In the import directory created by DSPB (DSPBuilder_<modelname>_import) when you compile (which will fail), create a file called aaa_add.tcl (alphabetically first so you can guarantee it gets run before others). 

2. Add the following lines to that file: 

set quartus_dir $::env(QUARTUS_ROOTDIR) if { set dspba_hdl_dir $::env(DSPBA_HDL_DIR) } else { set dspba_hdl_dir $quartus_dir/dspba/Libraries } set_global_assignment -name VHDL_FILE $dspba_hdl_dir/vhdl/fpc/hcc_package.vhd set_global_assignment -name VHDL_FILE $dspba_hdl_dir/vhdl/fpc/math_package.vhd set_global_assignment -name VHDL_FILE $dspba_hdl_dir/vhdl/fpc/hcc_implementation.vhd set_global_assignment -name VHDL_FILE $dspba_hdl_dir/vhdl/fpc/math_implementation.vhd set_global_assignment -name VHDL_FILE $dspba_hdl_dir/vhdl/fpc/fpc_library_package.vhd set_global_assignment -name VHDL_FILE $dspba_hdl_dir/vhdl/fpc/fpc_library.vhd 

3. Create another file called aaa_add_msim.tcl. 

4. Add the following lines: 

set base_dir "<path to your DSPBA rtl directory>" set quartus_dir $::env(QUARTUS_ROOTDIR) if { set dspba_hdl_dir $::env(DSPBA_HDL_DIR) } else { set dspba_hdl_dir $quartus_dir/dspba/Libraries } file delete -force $base_dir/fpc vlib fpc vmap fpc $base_dir/fpc vcom -quiet -93 -work $base_dir/fpc "$dspba_hdl_dir/vhdl/fpc/hcc_package.vhd" vcom -quiet -93 -work $base_dir/fpc "$dspba_hdl_dir/vhdl/fpc/math_package.vhd" vcom -quiet -93 -work $base_dir/fpc "$dspba_hdl_dir/vhdl/fpc/hcc_implementation.vhd" vcom -quiet -93 -work $base_dir/fpc "$dspba_hdl_dir/vhdl/fpc/math_implementation.vhd" vcom -quiet -93 -work $base_dir/fpc "$dspba_hdl_dir/vhdl/fpc/fpc_library_package.vhd" vcom -quiet -93 -work $base_dir/fpc "$dspba_hdl_dir/vhdl/fpc/fpc_library.vhd" 

 

Filling in <path to your DSPBA rtl directory> as appropriate.
0 Kudos
Altera_Forum
Honored Contributor II
582 Views

Hi dabuk, 

You're awesome, thank you so much for your reply! So far the tcl files work great.  

Best Regards, 

rushale
0 Kudos
Altera_Forum
Honored Contributor II
582 Views

I found I had to do a few other things to get the Standard Blockset Test-Bench to work: 

 

First I had to make sure the "Turn on coverage in testbenches" option on the Advanced Blockset Control block was off. 

Then I had to alter the above aaa_add_msim.tcl file a little. When specifying the directory paths, make sure only forward-slashes are used - no back-slashes 

 

 

 

--- Quote Start ---  

set base_dir "<path to your DSPBA rtl directory>"# this is still required for elsewhere 

set tbbase_dir "<path to your DSPB testbench directory>"# this is the one starting tb_  

set quartus_dir $::env(QUARTUS_ROOTDIR) 

if [info exists ::env(DSPBA_HDL_DIR)] { 

set dspba_hdl_dir $::env(DSPBA_HDL_DIR) 

} else { 

set dspba_hdl_dir $quartus_dir/dspba/Libraries 

file delete -force $tbbase_dir/fpc 

vlib fpc 

vmap fpc $tbbase_dir/fpc 

vcom -quiet -93 -work $tbbase_dir/fpc "$dspba_hdl_dir/vhdl/fpc/hcc_package.vhd" 

vcom -quiet -93 -work $tbbase_dir/fpc "$dspba_hdl_dir/vhdl/fpc/math_package.vhd" 

vcom -quiet -93 -work $tbbase_dir/fpc "$dspba_hdl_dir/vhdl/fpc/hcc_implementation.vhd" 

vcom -quiet -93 -work $tbbase_dir/fpc "$dspba_hdl_dir/vhdl/fpc/math_implementation.vhd" 

vcom -quiet -93 -work $tbbase_dir/fpc "$dspba_hdl_dir/vhdl/fpc/fpc_library_package.vhd" 

vcom -quiet -93 -work $tbbase_dir/fpc "$dspba_hdl_dir/vhdl/fpc/fpc_library.vhd" 

--- Quote End ---  

0 Kudos
Altera_Forum
Honored Contributor II
582 Views

Thank you sharkster! I'll try this if there are any further problems. So far so good. :) 

 

Best Regards, 

RUSHALE
0 Kudos
Reply