VIP Clocked Video Out Problem

[Altera_Forum]

I am having some problems with the VIP CVO IP. My QSYS core frequency is 100Mhz 

But my CVO IP output must run at a different frequency. Initially I used 44.8Mhz  And it seemed to work ok. However, when I doubled the CVO clock in to 89.6   It stopped working – the LPDDR2 would not calibrate, etc. etc. Again, I’m applying  An external clock to the CVO (ITC) expecting it to sync between the internal 100Mhz  And external 89.6Mhz. I did not configure for a control port and simply relying on  The width/height, etc. setting which are not standard. Does it mean that the system   Can’t keep up with to 89.6? should I increase it to 120Mhz.    Thanks,  S. 

[Altera_Forum]

What does the FIFO-Underflow signal say? If you have an underflow, maybe an increasing of the clock would help, but please share some insights of your whole systemdesign to give us a better view of maybe improvements regarding your design. 

 And maybe you want to have a look to the timing-analysis of your design...

[Altera_Forum]

Thanks Taz1984, I got it all working ! Instead of using the external clock I simply ran the ITC/CVO on the same streaming clock which I increased to match 

to the external clock freq. I still have in the design the "Sequencer IP" which requires a license... it does not do very much other than discard the upper byte of the 32bit coming in from the Frame-Reader and going to the CVO. Can I do away with not using it? This is preventing me from putting the design into FLASH. My next task is loading an image into LPDDR but FAST. I am now using an external bridge (the Master on the Avalon-MM bus) to an SPI interface. It takes 20min to load into LPDDR... Any suggestions?

[Altera_Forum]

You may write your own sequencer to get rid of the one with license-fee, should not be that hard to write. 

 To give you a hint regarding the loading an image to the ddr, I need to understand your whole system-design first. -Which Chip do you use? An SoC with HPS, do you have a NIOS in your design? -Which width and height does the image has? -Do you just want to show an image, or several changing images, or a live-stream of a video source?

[Altera_Forum]

Thanks Taz. How do I write my own sequencer or any other Avalon ST module and integrate it into the lib? Are there any examples for doing that? 

 The main issue with loading the DDR in my case is that I don't have a NIOS II in the system. I use an external master/bridge, etc. this slows down the process because of the use of Python script. So I think that I'm going to add a NIOS II to the system and download the large image file using it. (1920*720*2=2764800pixels, *4bytes=11MegB per image) It would have been nice to download the image through using In-System Memory Editor but that is only for SRAM. The JTAG/SPI access way is too convoluted to use.  Thanks, Jacob

[Altera_Forum]

--- Quote Start ---  Thanks Taz1984, I got it all working ! Instead of using the external clock I simply ran the ITC/CVO on the same streaming clock which I increased to match to the external clock freq. I still have in the design the "Sequencer IP" which requires a license... it does not do very much other than discard the upper byte of the 32bit coming in from the Frame-Reader and going to the CVO. Can I do away with not using it? This is preventing me from putting the design into FLASH. My next task is loading an image into LPDDR but FAST. I am now using an external bridge (the Master on the Avalon-MM bus) to an SPI interface. It takes 20min to load into LPDDR... Any suggestions?  --- Quote End ---    Hi Shvitzer, Firstly it is not clear what you are doing. Secondly it is not clear which clock domains in the system you have.  Not talking about the Sequencer IP..what is that? Are you talking about the Color Plane Sequencer?  Next, how do you use LPDDR? Do you put your frame there to be used by the Frame Reader? You connect your FR to LPDDR and use Nios II. It is cheap (E is free) and nasty .....

[Altera_Forum]

Yes, it is the Color Plane Sequencer. I am using the LPDDR to store an image which is read by the Frame-Reader, passed on to the Color Plane Sequencer and from there to the Clocked Video Output. This is a reloadable pattern generator. I now have only one clock of 89.6Mhz. To get the image into the LPDDR I use an External But Bridge which is controlled the SW on the PC via an SPI module-to-USB. The Color Plane Sequencer is the only module that requires a license. I was told that I have to buy the license for the VIP set. 

So I want to design my own Color Plane Sequencer. Is there a template/example for developing your own IP. I now added a NIOS II to the design and it runs SW. I tried to add the SD_Card_Avalon_interface. QSYS came back with the error: Altera_UP_SD_Card_Memory_Block.qip,cmp,bsf not found... This project is going to be axed soon if I don't solve these problems.

[Altera_Forum]

Shvitzer, AFAIK all VIP cores (not only CPS) require the license. Maybe CVO is the only exception. It is not clear why you need the Sequencer. Usually, it is used to combine two avalon-st streams into one or reorganize the sequence of the colour planes. You have only one stream...so not the first case. and you get your image from the Frame reader which allows you to specify the color sequence you need on the output. 

The SD card controller requires the license too afaik....

[Altera_Forum]

Thanks uilka_b for replying. Yes I agree with you, I did not see the need for the CPS but when I remove it and go directly from the Frame Reader to the CVO it does not work. QSYS is happy 

but it does not work. From what I can see, the CPS receives 4 bytes of which only 3 are needed (23:0 = RGB) and the 4th one (31:24) is discarded. I would love to get rid of it, what am I missing? Again, if I go directly from the Frame Reader to the CVO 3 color planes all the way things don't work, I don't get any license warning and no "time limited" .sof. But it does not work. Can someone explain this?  The SD card controller from TERASIC simply uses 3 PIOs and some SW - don't need Altera's IP.  Thanks, Guys

[Altera_Forum]

--- Quote Start ---  Thanks uilka_b for replying. Yes I agree with you, I did not see the need for the CPS but when I remove it and go directly from the Frame Reader to the CVO it does not work. QSYS is happy but it does not work. From what I can see, the CPS receives 4 bytes of which only 3 are needed (23:0 = RGB) and the 4th one (31:24) is discarded. I would love to get rid of it, what am I missing? Again, if I go directly from the Frame Reader to the CVO 3 color planes all the way things don't work, I don't get any license warning and no "time limited" .sof. But it does not work. Can someone explain this?  The SD card controller from TERASIC simply uses 3 PIOs and some SW - don't need Altera's IP.  Thanks, Guys  --- Quote End ---    It is strange that the Frame reader generates 4 bytes. You can specify in the Frame Reader GUI to generate 3 color planes (in sequence or parallel), so it will be 3*8=24. Usually to test your VIP design step-by-step first you create just a simple Test Pattern-> CVO path to test your CVO. Next step is to add your FR + Test Pattern as a second channel through the Mixer to CVO when you can enable and disable Mixer layers and change your FR settings on the fly to find the best settings.  Regarding Terasic SD card controller..... if it just 3 Altera PIO blocks getting Altera_UP_SD_Card_Memory_Block.qip error message is too strange. Are you sure you know what you are doing? Good luck

[Altera_Forum]

Thank you guys for trying to help, however, I am getting more questions than answers here and little or no help. Let me clarify something: my VIP design works now, however, I can not afford the license fee for the CPS so I am looking for ways to get rid of it or design my own. The FR reads 32bit from DDR of which only 3*8=24 are needed that is where the CPS comes in to discard the upper 8 bits and stream only 24bits to the CVO. Yes, I can configure the FR to send only 3 color planes directly to the CVO, all compile, but no video comes out!!! 

 Regarding the SD card controller (nothing to do with the above) Quartus/QSYS is missing the files I mentioned. Just Google the problem and you will see that others ran into the same problem. Please don't ask me if I know what I am doing, that is rude. Try to answer the question only if you can.

[Altera_Forum]

--- Quote Start ---  The FR reads 32bit from DDR of which only 3*8=24 are needed that is where the CPS comes in to discard the upper 8 bits and stream only 24bits to the CVO. Yes, I can configure the FR to send only 3 color planes directly to the CVO, all compile, but no video comes out!!!  --- Quote End ---   Did you make any others changes in project when you change FR configuration from 4 bytes to 3 bytes?

[Altera_Forum]

--- Quote Start ---  Thank you guys for trying to help, however, I am getting more questions than answers here and little or no help. Let me clarify something: my VIP design works now, however, I can not afford the license fee for the CPS so I am looking for ways to get rid of it or design my own. The FR reads 32bit from DDR of which only 3*8=24 are needed that is where the CPS comes in to discard the upper 8 bits and stream only 24bits to the CVO. Yes, I can configure the FR to send only 3 color planes directly to the CVO, all compile, but no video comes out!!!  Regarding the SD card controller (nothing to do with the above) Quartus/QSYS is missing the files I mentioned. Just Google the problem and you will see that others ran into the same problem. Please don't ask me if I know what I am doing, that is rude. Try to answer the question only if you can.  --- Quote End ---    Shvitzer, I am answering here because I have experience working with the Frame Reader and I never used CPS. Just trying to help. You have to find the root of the problem in using FR. It is parameterized using Nios II. Small Nios is free and doesn't use too much logic.  Regarding SD card I didn't mean to be rude. I just asked if you know what you doing. If yes then It is a quartus BUG and you should look for a fix. Check the Quartus version and look at the knowledge database. Probs you can find these files and put them manually to the Qsys synthesis directory as a temporarily fix.