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Altera_Forum
Honored Contributor I
755 Views

VIP FMax

Is the FMax for VIP cores characterized in any documentation for any specific device families? 

I am trying to run my SOPC builder system, comprising a number of VIP cores in Arria2 GX I5 device. I have constrained the system clock to be 185.7 MHz, but it seems to be failing this timing constraint very badly (slack > 3 ns!). 

 

Does anybody have a feel for the FMax for the VIP suite in this device family (or any other device family!)?  

 

Thanks
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Altera_Forum
Honored Contributor I
34 Views

You can find it in the VIP datasheet. Some of the cores run around 150MHz. Also check your SDC to make sure clock groups were set right.

Altera_Forum
Honored Contributor I
34 Views

Thankyou - I have now seen this information in the datasheet. It seems to give rough characterizations for Cyclone and Stratix devices. I am guessing that the Arria2 devices must be somewhere in between? 

Assuming this, it would seem that 187 MHz may be on the hairy edge for this family. In a fairly full design, I suppose meeting timing may be a challenge anyway. Pipelining would be the normal approach, but from my understanding, 11.1 SOPC Builder does not really support the option of insertion of pipelining stages for all IP blocks. My understanding is that QSys offers more options on this front. Am I right?
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