FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

VIP Frame buffer not reading

Altera_Forum
Honored Contributor II
1,177 Views

Hi, 

 

We are currently investigating an issue where our VIP frame buffer is not issuing any reads on the Master read port. 

 

We have a Frame buffer configured to drop/duplicate and drop errored frames. Also, it implements independant write/read master clocks to interface to the memory. 

 

It seems that there are frames being written in on the write master and the up stream component has the ready asserted, the GO bit is set but there is no read request started on the read master. 

 

This problem seems to go and come with different compiles and if we keep configuring the pipelines - then it might start working. 

 

This does sound like a timing issue but the timing looks correct and the proper .sdc is referenced. The core is encrypted so it is impossible to track down the issue further... Has anyone seen anything like this? 

 

thx, 

 

paul
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
312 Views

Hi, 

 

What happens if you uncheck the tick box to drop errored frames? If the read side works consistently after such a change but you cannot get a proper video output from your system then it probably means that the frame buffer is receiving invalid control packets and/or image packets with incorrect size. 

 

There could be a configuration issue with one of the core upstream. Also, check for overflow at the input if you are using the VIP Clocked Video Input.  

 

vgs
0 Kudos
Reply