FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6586 Discussions

VIP suite: control synchronizer

Altera_Forum
Honored Contributor II
‎12-21-2012 02:04 AM
1,026 Views

Regarding the Video Control Synchronizer block. 

 

Can a Ctrl Sync be used to control multiple slave IP blocks? If so how does it distinguish between them when writing to their registers? I guess I mean this - does the Ctrl Sync Avalon Memory Mapped Master port use the address map as in the QSys system?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.