FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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6162 Discussions

VIP suite: control synchronizer

Honored Contributor II

Regarding the Video Control Synchronizer block. 


Can a Ctrl Sync be used to control multiple slave IP blocks? If so how does it distinguish between them when writing to their registers? I guess I mean this - does the Ctrl Sync Avalon Memory Mapped Master port use the address map as in the QSys system?
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