FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
6162 Discussions

VIP suite: control synchronizer

Altera_Forum
Honored Contributor II
818 Views

Regarding the Video Control Synchronizer block. 

 

Can a Ctrl Sync be used to control multiple slave IP blocks? If so how does it distinguish between them when writing to their registers? I guess I mean this - does the Ctrl Sync Avalon Memory Mapped Master port use the address map as in the QSys system?
0 Kudos
0 Replies
Reply