Verilog SDR SDRAM Controller without NOIS

[Altera_Forum]

Hi  

 I need a Verilog SDR SDRAM controller that is not part of Nois. Also one that does not require anything more than the Quartus web edition. IE One that is FREE!! I have read many suggestions on this forum but have not come accross anything usable yet. Being new to all of this I am also looking for a design that is fairly simple. I can do the initiallizing of the Sdram with an external CPU, this might make the design easier??? Any suggestions?

[Altera_Forum]

Boy you're not asking for much are you? I would say that if you can't find one on opencores.org, you'll likely have to write it yourself.  

SDR isn't too bad but still you're probably looking at a few weeks of develoment time. The physical layer for SDR is easy but you'll still have to come up with the controller state machine.  You can understand why most companies don't just give this stuff away.  Jake